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| author | caiyinyu <caiyinyu@loongson.cn> | 2022-08-10 10:21:46 +0800 |
|---|---|---|
| committer | caiyinyu <caiyinyu@loongson.cn> | 2022-08-12 09:30:56 +0800 |
| commit | 1c9bc1b6e50293a1b7037a7bfbf835868a55baed (patch) | |
| tree | 33bcdaa52d913e1f09b959cba4eac20e6a11540f /sysdeps/loongarch/setjmp.S | |
| parent | 12182ba18dabda791a4f63a11ee2e9d828f40f9b (diff) | |
| download | glibc-1c9bc1b6e50293a1b7037a7bfbf835868a55baed.tar.gz glibc-1c9bc1b6e50293a1b7037a7bfbf835868a55baed.tar.xz glibc-1c9bc1b6e50293a1b7037a7bfbf835868a55baed.zip | |
LoongArch: Add pointer mangling support.
Diffstat (limited to 'sysdeps/loongarch/setjmp.S')
| -rw-r--r-- | sysdeps/loongarch/setjmp.S | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/sysdeps/loongarch/setjmp.S b/sysdeps/loongarch/setjmp.S index 3afb9f3948..ec4ddc72da 100644 --- a/sysdeps/loongarch/setjmp.S +++ b/sysdeps/loongarch/setjmp.S @@ -29,8 +29,15 @@ ENTRY (setjmp) END (setjmp) ENTRY (__sigsetjmp) +#ifdef PTR_MANGLE + PTR_MANGLE (t0, ra, t1, t2) + REG_S t0, a0, 0*SZREG + PTR_MANGLE2 (t0, sp, t1) + REG_S t0, a0, 1*SZREG +#else REG_S ra, a0, 0*SZREG REG_S sp, a0, 1*SZREG +#endif REG_S x, a0, 2*SZREG REG_S fp, a0, 3*SZREG REG_S s0, a0, 4*SZREG |