Add float128 support for ia64.

This patch enables float128 support for ia64, so that all the
configurations where GCC supports _Float128 / __float128 as an
ABI-distinct type now have glibc support as well.  bits/floatn.h
declares the support to be available for GCC 4.4 and later, which is
when the libgcc support was added.  The removal of
sysdeps/ia64/fpu/k_rem_pio2.c is because the generic k_rem_pio2.c
defines a function required by the float128 code.

Tested (compilation only) with build-many-glibcs.py for ia64 (GCC 6
and GCC 7).

Given how long it is since libm-test-ulps has been updated for ia64, I
think truncating the file and regenerating it from scratch would be a
good idea when doing a regeneration to add float128 ulps.  I expect
various ia64 libm issues (at least some already filed in Bugzilla) to
result in test failures even after ulps regeneration, but hopefully
the float128 code will pass tests as it's the same as used on other
architectures.

	* sysdeps/ia64/Implies: Add ieee754/float128.
	* sysdeps/ia64/bits/floatn.h: New file.
	* sysdeps/ia64/float128-abi.h: Likewise.
	* manual/math.texi (Mathematics): Document support for _Float128
	on ia64.
	* sysdeps/ia64/Makefile [$(subdir) = math] (CPPFLAGS): Append to
	Makefile variable.
	* sysdeps/ia64/fpu/e_sqrtf128.c: New file.
	* sysdeps/ia64/fpu/k_rem_pio2.c: Remove file.
	* sysdeps/ia64/fpu/sfp-machine.h: New file.  Based on libgcc.
	* sysdeps/ia64/math-tests.h: New file.
	* math/libm-test-support.h (XFAIL_FLOAT128_PAYLOAD): Also define
	based on TEST_COND_binary128 for [__ia64__].
	* sysdeps/unix/sysv/linux/ia64/libc.abilist: Update.
	* sysdeps/unix/sysv/linux/ia64/libm.abilist: Likewise,

1 files changed, 100 insertions, 0 deletions

diff --git a/sysdeps/ia64/fpu/sfp-machine.h b/sysdeps/ia64/fpu/sfp-machine.h
new file mode 100644
index 0000000000..45e844d3da
--- /dev/null
+++ b/sysdeps/ia64/fpu/sfp-machine.h
@@ -0,0 +1,100 @@
+#define _FP_W_TYPE_SIZE		64
+#define _FP_W_TYPE		unsigned long
+#define _FP_WS_TYPE		signed long
+#define _FP_I_TYPE		long
+
+typedef int TItype __attribute__ ((mode (TI)));
+typedef unsigned int UTItype __attribute__ ((mode (TI)));
+
+#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype))
+
+/* The type of the result of a floating point comparison.  This must
+   match `__libgcc_cmp_return__' in GCC for the target.  */
+typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
+#define CMPtype __gcc_CMPtype
+
+#define _FP_MUL_MEAT_Q(R,X,Y)				\
+  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
+
+#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
+
+#define _FP_NANFRAC_S		_FP_QNANBIT_S
+#define _FP_NANFRAC_D		_FP_QNANBIT_D
+#define _FP_NANFRAC_E		_FP_QNANBIT_E, 0
+#define _FP_NANFRAC_Q		_FP_QNANBIT_Q, 0
+
+#define _FP_KEEPNANFRACP	1
+#define _FP_QNANNEGATEDP 0
+
+#define _FP_NANSIGN_S		1
+#define _FP_NANSIGN_D		1
+#define _FP_NANSIGN_E		1
+#define _FP_NANSIGN_Q		1
+
+/* Here is something Intel misdesigned: the specs don't define
+   the case where we have two NaNs with same mantissas, but
+   different sign. Different operations pick up different NaNs.  */
+#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)			\
+  do {								\
+    if (_FP_FRAC_GT_##wc(X, Y)					\
+	|| (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*')))	\
+      {								\
+	R##_s = X##_s;						\
+	_FP_FRAC_COPY_##wc(R,X);				\
+      }								\
+    else							\
+      {								\
+	R##_s = Y##_s;						\
+	_FP_FRAC_COPY_##wc(R,Y);				\
+      }								\
+    R##_c = FP_CLS_NAN;						\
+  } while (0)
+
+#define FP_EX_INVALID		0x01
+#define FP_EX_DENORM		0x02
+#define FP_EX_DIVZERO		0x04
+#define FP_EX_OVERFLOW		0x08
+#define FP_EX_UNDERFLOW		0x10
+#define FP_EX_INEXACT		0x20
+#define FP_EX_ALL \
+	(FP_EX_INVALID | FP_EX_DENORM | FP_EX_DIVZERO | FP_EX_OVERFLOW \
+	 | FP_EX_UNDERFLOW | FP_EX_INEXACT)
+
+#define _FP_TININESS_AFTER_ROUNDING 1
+
+void __sfp_handle_exceptions (int);
+
+#define FP_HANDLE_EXCEPTIONS			\
+  do {						\
+    if (__builtin_expect (_fex, 0))		\
+      __sfp_handle_exceptions (_fex);		\
+  } while (0);
+
+#define FP_TRAPPING_EXCEPTIONS	(~_fcw & FP_EX_ALL)
+
+#define FP_RND_NEAREST		0
+#define FP_RND_ZERO		0xc00L
+#define FP_RND_PINF		0x800L
+#define FP_RND_MINF		0x400L
+
+#define FP_RND_MASK		0xc00L
+
+#define _FP_DECL_EX \
+  unsigned long int _fcw __attribute__ ((unused)) = FP_RND_NEAREST
+
+#define FP_INIT_ROUNDMODE					\
+  do {								\
+    __asm__ __volatile__ ("mov.m %0 = ar.fpsr" : "=r" (_fcw));	\
+  } while (0)
+
+#define FP_ROUNDMODE		(_fcw & FP_RND_MASK)
+
+#define	__LITTLE_ENDIAN	1234
+#define	__BIG_ENDIAN	4321
+
+#define __BYTE_ORDER __LITTLE_ENDIAN
+
+/* Define ALIASNAME as a strong alias for NAME.  */
+#define strong_alias(name, aliasname) _strong_alias(name, aliasname)
+#define _strong_alias(name, aliasname) \
+  extern __typeof (name) aliasname __attribute__ ((alias (#name)));