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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-05-09 10:39:49 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2019-01-03 18:38:15 -0200 |
| commit | 0b13e25581afb4ce95373f18249b91c104280a13 (patch) | |
| tree | 8ddaf3ba022a31225b13bc2edaa9eb26b74bf5da /sysdeps/i386/nptl | |
| parent | 85c828a4626adda906f8844dc9c5a166c72d4f7d (diff) | |
| download | glibc-0b13e25581afb4ce95373f18249b91c104280a13.tar.gz glibc-0b13e25581afb4ce95373f18249b91c104280a13.tar.xz glibc-0b13e25581afb4ce95373f18249b91c104280a13.zip | |
i386: Remove bogus THREAD_ATOMIC_* macros
The x86 defines optimized THREAD_ATOMIC_* macros where reference always the current thread instead of the one indicated by input 'descr' argument. It work as long the input is the self thread pointer, however it generates wrong code if the semantic is to set a bit atomicialy from another thread. This is not an issue for current GLIBC usage, however the new cancellation code expects that some synchronization code to atomically set bits from different threads. If some usage indeed proves to be a hotspot we can add an extra macro with a more descriptive name (THREAD_ATOMIC_BIT_SET_SELF for instance) where i386 might optimize it. Checked on i686-linux-gnu. * sysdeps/i686/nptl/tls.h (THREAD_ATOMIC_CMPXCHG_VAL, THREAD_ATOMIC_AND, THREAD_ATOMIC_BIT_SET): Remove macros.
Diffstat (limited to 'sysdeps/i386/nptl')
| -rw-r--r-- | sysdeps/i386/nptl/tls.h | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/sysdeps/i386/nptl/tls.h b/sysdeps/i386/nptl/tls.h index 5a528fc1de..85a4b42bce 100644 --- a/sysdeps/i386/nptl/tls.h +++ b/sysdeps/i386/nptl/tls.h @@ -362,43 +362,6 @@ tls_fill_user_desc (union user_desc_init *desc, }}) -/* Atomic compare and exchange on TLS, returning old value. */ -#define THREAD_ATOMIC_CMPXCHG_VAL(descr, member, newval, oldval) \ - ({ __typeof (descr->member) __ret; \ - __typeof (oldval) __old = (oldval); \ - if (sizeof (descr->member) == 4) \ - asm volatile (LOCK_PREFIX "cmpxchgl %2, %%gs:%P3" \ - : "=a" (__ret) \ - : "0" (__old), "r" (newval), \ - "i" (offsetof (struct pthread, member))); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); \ - __ret; }) - - -/* Atomic logical and. */ -#define THREAD_ATOMIC_AND(descr, member, val) \ - (void) ({ if (sizeof ((descr)->member) == 4) \ - asm volatile (LOCK_PREFIX "andl %1, %%gs:%P0" \ - :: "i" (offsetof (struct pthread, member)), \ - "ir" (val)); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); }) - - -/* Atomic set bit. */ -#define THREAD_ATOMIC_BIT_SET(descr, member, bit) \ - (void) ({ if (sizeof ((descr)->member) == 4) \ - asm volatile (LOCK_PREFIX "orl %1, %%gs:%P0" \ - :: "i" (offsetof (struct pthread, member)), \ - "ir" (1 << (bit))); \ - else \ - /* Not necessary for other sizes in the moment. */ \ - abort (); }) - - /* Set the stack guard field in TCB head. */ #define THREAD_SET_STACK_GUARD(value) \ THREAD_SETMEM (THREAD_SELF, header.stack_guard, value) |