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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-04-16 08:18:23 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-04-16 17:24:31 -0300 |
| commit | 743b9c2a98426fb40f8ffee3529c8870bc5300f5 (patch) | |
| tree | f050338793677c5b1b2cd681d40c80a1be44ab08 /sysdeps/arm/armv6t2/memchr.S | |
| parent | 326e74e7c18ab12ac8e4b67cce295d32fcc1cf68 (diff) | |
| download | glibc-743b9c2a98426fb40f8ffee3529c8870bc5300f5.tar.gz glibc-743b9c2a98426fb40f8ffee3529c8870bc5300f5.tar.xz glibc-743b9c2a98426fb40f8ffee3529c8870bc5300f5.zip | |
arm: Remove ununsed ARM code in optimized implementation
This patch removes the ununsed ARM code path for armv6t2 memchr and strlen and armv7 memch and strcmp. In all implementation, the ARM code is not used in any possible build (unless glibc is explicit build with the non-documented NO_THUMB compiler flag) and for armv7 the resulting code either produces wrong results (memchr) and throw build error (strcmp). Checked on arm-linux-gnueabihf built targeting both armv6 and armv7. * sysdeps/arm/armv6t2/memchr.S (memchr): Remove ARM code path. * sysdeps/arm/armv6t2/strlen.S (memchr): Likewise. * sysdeps/arm/armv7/multiarch/memchr_neon.S (memchr): Likewise. * sysdeps/arm/armv7/strcmp.S (strcmp): Likewise.
Diffstat (limited to 'sysdeps/arm/armv6t2/memchr.S')
| -rw-r--r-- | sysdeps/arm/armv6t2/memchr.S | 23 |
1 files changed, 0 insertions, 23 deletions
diff --git a/sysdeps/arm/armv6t2/memchr.S b/sysdeps/arm/armv6t2/memchr.S index bdd385b572..1d6eee0a11 100644 --- a/sysdeps/arm/armv6t2/memchr.S +++ b/sysdeps/arm/armv6t2/memchr.S @@ -42,12 +42,8 @@ .syntax unified .text -#ifdef NO_THUMB - .arm -#else .thumb .thumb_func -#endif .global memchr .type memchr,%function ENTRY(memchr) @@ -91,22 +87,14 @@ ENTRY(memchr) 15: ldrd r4,r5, [r0],#8 -#ifndef NO_THUMB subs r6, r6, #8 -#endif eor r4,r4, r1 @ Get it so that r4,r5 have 00's where the bytes match the target eor r5,r5, r1 uadd8 r4, r4, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 sel r4, r3, r7 @ bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION uadd8 r5, r5, r7 @ Parallel add 0xff - sets the GE bits for anything that wasn't 0 sel r5, r4, r7 @ chained....bytes are 00 for none-00 bytes, or ff for 00 bytes - NOTE INVERSION -#ifndef NO_THUMB cbnz r5, 60f -#else - cmp r5, #0 - bne 60f - subs r6, r6, #8 -#endif bne 15b @ (Flags from the subs above) If not run out of bytes then go around again pop {r4,r5,r6,r7} @@ -120,24 +108,13 @@ ENTRY(memchr) and r2,r2,#7 @ Leave the count remaining as the number after the double words have been done 20: -#ifndef NO_THUMB cbz r2, 40f @ 0 length or hit the end already then not found -#else - cmp r2, #0 - beq 40f -#endif 21: @ Post aligned section, or just a short call ldrb r3,[r0],#1 -#ifndef NO_THUMB subs r2,r2,#1 eor r3,r3,r1 @ r3 = 0 if match - doesn't break flags from sub cbz r3, 50f -#else - eors r3, r3, r1 - beq 50f - subs r2, r2, #1 -#endif bne 21b @ on r2 flags 40: |