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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-03-06 10:19:32 -0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-03-15 05:43:26 -0700 |
| commit | f53ffc9b90cbd92fa5518686daf4091bdd1d4889 (patch) | |
| tree | 35e4c6a7aa32823135a4ceafdcde998e976727e2 /sysdeps/alpha/bits | |
| parent | 332421312576bd7095e70589154af99b124dd2d1 (diff) | |
| download | glibc-f53ffc9b90cbd92fa5518686daf4091bdd1d4889.tar.gz glibc-f53ffc9b90cbd92fa5518686daf4091bdd1d4889.tar.xz glibc-f53ffc9b90cbd92fa5518686daf4091bdd1d4889.zip | |
x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]
commit 2d651eb9265d1366d7b9e881bfddd46db9c1ecc4
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Fri Sep 18 07:55:14 2020 -0700
x86: Move x86 processor cache info to cpu_features
missed _SC_LEVEL1_ICACHE_LINESIZE.
1. Add level1_icache_linesize to struct cpu_features.
2. Initialize level1_icache_linesize by calling handle_intel,
handle_zhaoxin and handle_amd with _SC_LEVEL1_ICACHE_LINESIZE.
3. Return level1_icache_linesize for _SC_LEVEL1_ICACHE_LINESIZE.
Reviewed-by: Carlos O'Donell <carlos@redhat.com>
Diffstat (limited to 'sysdeps/alpha/bits')
0 files changed, 0 insertions, 0 deletions