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| author | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2018-08-15 23:01:33 +0530 |
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| committer | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2018-08-15 23:01:33 +0530 |
| commit | 436e4d5b965abe592d26150cb518accf9ded8fe4 (patch) | |
| tree | 59ff500e4e7c2f63c1eb393f8dbc0af2ebbb774e /sysdeps/aarch64/strlen.S | |
| parent | 126c4e3f804881f9fbc4eb71787f41793d2d7be5 (diff) | |
| download | glibc-436e4d5b965abe592d26150cb518accf9ded8fe4.tar.gz glibc-436e4d5b965abe592d26150cb518accf9ded8fe4.tar.xz glibc-436e4d5b965abe592d26150cb518accf9ded8fe4.zip | |
[aarch64] Add an ASIMD variant of strlen for falkor
This variant of strlen uses vector loads and operations to reduce the size of the code and also eliminate the non-ascii fallback. This works very well for falkor because of its two vector units and efficient vector ops. In the best case it reduces latency of cases in bench-strlen by 48%, with gains throughout the benchmark. strlen-walk also sees uniform gains in the 5%-15% range. Overall the routine appears to work better than the stock one for falkor regardless of the benchmark, length of string or cache state. The same cannot be said of a53 and a72 though. a53 performance was greatly reduced and for a72 it was a bit of a mixed bag, slightly on the negative side but I reckon it might be fast in some situations. * sysdeps/aarch64/strlen.S (__strlen): Rename to STRLEN. [!STRLEN](STRLEN): Set to __strlen. * sysdeps/aarch64/multiarch/strlen.c: New file. * sysdeps/aarch64/multiarch/strlen_generic.S: Likewise. * sysdeps/aarch64/multiarch/strlen_asimd.S: Likewise. * sysdeps/aarch64/multiarch/ifunc-impl-list.c (__libc_ifunc_impl_list): Add strlen. * sysdeps/aarch64/multiarch/Makefile (sysdep_routines): Add strlen_generic and strlen_asimd. Reviewed-By: szabolcs.nagy@arm.com CC: pinskia@gmail.com
Diffstat (limited to 'sysdeps/aarch64/strlen.S')
| -rw-r--r-- | sysdeps/aarch64/strlen.S | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/sysdeps/aarch64/strlen.S b/sysdeps/aarch64/strlen.S index eb773ef532..521ebc3b75 100644 --- a/sysdeps/aarch64/strlen.S +++ b/sysdeps/aarch64/strlen.S @@ -23,6 +23,10 @@ * ARMv8-a, AArch64, unaligned accesses, min page size 4k. */ +#ifndef STRLEN +# define STRLEN __strlen +#endif + /* To test the page crossing code path more thoroughly, compile with -DTEST_PAGE_CROSS - this will force all calls through the slower entry path. This option is not intended for production use. */ @@ -84,7 +88,7 @@ whether the first fetch, which may be misaligned, crosses a page boundary. */ -ENTRY_ALIGN (__strlen, 6) +ENTRY_ALIGN (STRLEN, 6) DELOUSE (0) DELOUSE (1) and tmp1, srcin, MIN_PAGE_SIZE - 1 @@ -215,6 +219,6 @@ L(page_cross): csel data1, data1, tmp4, eq csel data2, data2, tmp2, eq b L(page_cross_entry) -END (__strlen) -weak_alias (__strlen, strlen) +END (STRLEN) +weak_alias (STRLEN, strlen) libc_hidden_builtin_def (strlen) |