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| author | Hongbo Zhang <hongbo.zhang@linaro.org> | 2018-06-12 21:29:11 +0530 |
|---|---|---|
| committer | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2018-06-12 21:29:11 +0530 |
| commit | fc2ba8037dec486c0557eba0b807060ace857701 (patch) | |
| tree | 07932c664817a919bd56a432cd59af8cff38096b /sysdeps/aarch64/multiarch/memcpy.c | |
| parent | 5aad5f617892e75d91d4c8fb7594ff35b610c042 (diff) | |
| download | glibc-fc2ba8037dec486c0557eba0b807060ace857701.tar.gz glibc-fc2ba8037dec486c0557eba0b807060ace857701.tar.xz glibc-fc2ba8037dec486c0557eba0b807060ace857701.zip | |
aarch64: add HXT Phecda core memory operation ifuncs
Phecda is HXT semiconductor's CPU core, this patch adds memory operation ifuncs for it: sharing the same optimized implementation with Qualcomm's Falkor core. 2018-06-07 Minfeng Kang <minfeng.kang@hxt-semitech.com> Hongbo Zhang <hongbo.zhang@linaro.org> * sysdeps/aarch64/multiarch/memcpy.c (libc_ifunc): reuse __memcpy_falkor for phecda core. * sysdeps/aarch64/multiarch/memmove.c (libc_ifunc): reuse __memmove_falkor for phecda core. * sysdeps/aarch64/multiarch/memset.c (libc_ifunc): reuse __memset_falkor for phecda core. * sysdeps/unix/sysv/linux/aarch64/cpu-features.c: add MIDR entry for phecda core. * sysdeps/unix/sysv/linux/aarch64/cpu-features.h (IS_PHECDA): add macro to identify phecda core.
Diffstat (limited to 'sysdeps/aarch64/multiarch/memcpy.c')
| -rw-r--r-- | sysdeps/aarch64/multiarch/memcpy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sysdeps/aarch64/multiarch/memcpy.c b/sysdeps/aarch64/multiarch/memcpy.c index b94c655f9d..4a04a63b0f 100644 --- a/sysdeps/aarch64/multiarch/memcpy.c +++ b/sysdeps/aarch64/multiarch/memcpy.c @@ -36,7 +36,7 @@ extern __typeof (__redirect_memcpy) __memcpy_falkor attribute_hidden; libc_ifunc (__libc_memcpy, (IS_THUNDERX (midr) ? __memcpy_thunderx - : (IS_FALKOR (midr) + : (IS_FALKOR (midr) || IS_PHECDA (midr) ? __memcpy_falkor : (IS_THUNDERX2 (midr) || IS_THUNDERX2PA (midr) ? __memcpy_thunderx2 |