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authorWilco Dijkstra <wdijkstr@arm.com>2015-08-05 15:03:08 +0100
committerWilco Dijkstra <wdijkstr@arm.com>2015-08-05 16:24:02 +0100
commit7b1c56e4834aa3b139fea39ded64a7e901be89a2 (patch)
tree1e134dab58412e1f8cd387a633fa12bedec2d7e6 /sysdeps/aarch64/fpu
parent3136eb7abd3e45a8622c0272181816c1a92e1f65 (diff)
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Improve feenableexcept performance - avoid an unnecessary FPCR read in case
the FPCR does not change. Also improve the logic of the return value.
Diffstat (limited to 'sysdeps/aarch64/fpu')
-rw-r--r--sysdeps/aarch64/fpu/feenablxcpt.c16
1 files changed, 7 insertions, 9 deletions
diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c
index 82ed0b623c..a0f736cc20 100644
--- a/sysdeps/aarch64/fpu/feenablxcpt.c
+++ b/sysdeps/aarch64/fpu/feenablxcpt.c
@@ -24,24 +24,22 @@ feenableexcept (int excepts)
 {
   fpu_control_t fpcr;
   fpu_control_t fpcr_new;
+  fpu_control_t updated_fpcr;
 
   _FPU_GETCW (fpcr);
   excepts &= FE_ALL_EXCEPT;
   fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT);
 
   if (fpcr != fpcr_new)
-    _FPU_SETCW (fpcr_new);
-
-  /* Trapping exceptions are optional in AArch64 the relevant enable
-     bits in FPCR are RES0 hence the absence of support can be
-     detected by reading back the FPCR and comparing with the required
-     value.  */
-  if (excepts)
     {
-      fpu_control_t updated_fpcr;
+      _FPU_SETCW (fpcr_new);
 
+      /* Trapping exceptions are optional in AArch64; the relevant enable
+	 bits in FPCR are RES0 hence the absence of support can be detected
+	 by reading back the FPCR and comparing with the required value.  */
       _FPU_GETCW (updated_fpcr);
-      if (((updated_fpcr >> FE_EXCEPT_SHIFT) & excepts) != excepts)
+
+      if (fpcr_new & ~updated_fpcr)
 	return -1;
     }