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authorJoe Ramsay <Joe.Ramsay@arm.com>2023-10-05 17:10:51 +0100
committerSzabolcs Nagy <szabolcs.nagy@arm.com>2023-10-23 15:00:45 +0100
commit067a34156c19fb3c53824e37d70820c0ce5b87b2 (patch)
treec0e5649d7892db1a9fc195adc8b381c01ab77544 /sysdeps/aarch64/fpu/vecmath_config.h
parenta8e3ab3074d448ff3e58ac8f850d955dfed830ad (diff)
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aarch64: Add vector implementations of log10 routines
A table is also added, which is shared between AdvSIMD and SVE log10.
Diffstat (limited to 'sysdeps/aarch64/fpu/vecmath_config.h')
-rw-r--r--sysdeps/aarch64/fpu/vecmath_config.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/vecmath_config.h b/sysdeps/aarch64/fpu/vecmath_config.h
index 3aa6c280aa..2c8e243236 100644
--- a/sysdeps/aarch64/fpu/vecmath_config.h
+++ b/sysdeps/aarch64/fpu/vecmath_config.h
@@ -62,4 +62,15 @@ extern const struct v_log2_data
   } table[1 << V_LOG2_TABLE_BITS];
 } __v_log2_data attribute_hidden;
 
+#define V_LOG10_TABLE_BITS 7
+extern const struct v_log10_data
+{
+  double poly[5];
+  double invln10, log10_2;
+  struct
+  {
+    double invc, log10c;
+  } table[1 << V_LOG10_TABLE_BITS];
+} __v_log10_data attribute_hidden;
+
 #endif