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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-10-05 17:10:52 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-10-23 15:00:45 +0100 |
| commit | 31aaf6fed986fade042f9ffe7535d8b3f2c173a2 (patch) | |
| tree | 5417d6dffd8eefa74a1506a792ed40330205ce31 /sysdeps/aarch64/fpu/test-float-sve-wrappers.c | |
| parent | 067a34156c19fb3c53824e37d70820c0ce5b87b2 (diff) | |
| download | glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.tar.gz glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.tar.xz glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.zip | |
aarch64: Add vector implementations of exp10 routines
Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
Diffstat (limited to 'sysdeps/aarch64/fpu/test-float-sve-wrappers.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/test-float-sve-wrappers.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c index 2ed8d0659a..885e58ac39 100644 --- a/sysdeps/aarch64/fpu/test-float-sve-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-sve-wrappers.c @@ -34,6 +34,7 @@ SVE_VECTOR_WRAPPER (cosf_sve, _ZGVsMxv_cosf) SVE_VECTOR_WRAPPER (expf_sve, _ZGVsMxv_expf) +SVE_VECTOR_WRAPPER (exp10f_sve, _ZGVsMxv_exp10f) SVE_VECTOR_WRAPPER (exp2f_sve, _ZGVsMxv_exp2f) SVE_VECTOR_WRAPPER (logf_sve, _ZGVsMxv_logf) SVE_VECTOR_WRAPPER (log10f_sve, _ZGVsMxv_log10f) |