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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-10-05 17:10:51 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-10-23 15:00:45 +0100 |
| commit | 067a34156c19fb3c53824e37d70820c0ce5b87b2 (patch) | |
| tree | c0e5649d7892db1a9fc195adc8b381c01ab77544 /sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | |
| parent | a8e3ab3074d448ff3e58ac8f850d955dfed830ad (diff) | |
| download | glibc-067a34156c19fb3c53824e37d70820c0ce5b87b2.tar.gz glibc-067a34156c19fb3c53824e37d70820c0ce5b87b2.tar.xz glibc-067a34156c19fb3c53824e37d70820c0ce5b87b2.zip | |
aarch64: Add vector implementations of log10 routines
A table is also added, which is shared between AdvSIMD and SVE log10.
Diffstat (limited to 'sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c index e8f7f47c67..6ced0d4488 100644 --- a/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c +++ b/sysdeps/aarch64/fpu/test-float-advsimd-wrappers.c @@ -27,6 +27,7 @@ VPCS_VECTOR_WRAPPER (cosf_advsimd, _ZGVnN4v_cosf) VPCS_VECTOR_WRAPPER (expf_advsimd, _ZGVnN4v_expf) VPCS_VECTOR_WRAPPER (exp2f_advsimd, _ZGVnN4v_exp2f) VPCS_VECTOR_WRAPPER (logf_advsimd, _ZGVnN4v_logf) +VPCS_VECTOR_WRAPPER (log10f_advsimd, _ZGVnN4v_log10f) VPCS_VECTOR_WRAPPER (log2f_advsimd, _ZGVnN4v_log2f) VPCS_VECTOR_WRAPPER (sinf_advsimd, _ZGVnN4v_sinf) VPCS_VECTOR_WRAPPER (tanf_advsimd, _ZGVnN4v_tanf) |