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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-12-19 16:44:01 +0000 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-12-20 08:41:25 +0000 |
| commit | cc0d77ba944cd4ce46c5f0e6d426af3057962ca5 (patch) | |
| tree | 840c09b10bcb0ad4f733e8cb4bce2acbd92e5945 /sysdeps/aarch64/fpu/tanf_advsimd.c | |
| parent | 3150cc0c9019bf9da841419f86dda8e7f26d676d (diff) | |
| download | glibc-cc0d77ba944cd4ce46c5f0e6d426af3057962ca5.tar.gz glibc-cc0d77ba944cd4ce46c5f0e6d426af3057962ca5.tar.xz glibc-cc0d77ba944cd4ce46c5f0e6d426af3057962ca5.zip | |
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines
Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/tanf_advsimd.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/tanf_advsimd.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sysdeps/aarch64/fpu/tanf_advsimd.c b/sysdeps/aarch64/fpu/tanf_advsimd.c index 4c8a7f740e..16b39e17a0 100644 --- a/sysdeps/aarch64/fpu/tanf_advsimd.c +++ b/sysdeps/aarch64/fpu/tanf_advsimd.c @@ -73,7 +73,7 @@ eval_poly (float32x4_t z, const struct data *d) Maximum error is 3.45 ULP: __v_tanf(-0x1.e5f0cap+13) got 0x1.ff9856p-1 want 0x1.ff9850p-1. */ -float32x4_t VPCS_ATTR V_NAME_F1 (tan) (float32x4_t x) +float32x4_t VPCS_ATTR NOINLINE V_NAME_F1 (tan) (float32x4_t x) { const struct data *d = ptr_barrier (&data); float32x4_t special_arg = x; @@ -127,3 +127,5 @@ float32x4_t VPCS_ATTR V_NAME_F1 (tan) (float32x4_t x) return special_case (special_arg, vbslq_f32 (pred_alt, inv_y, y), special); return vbslq_f32 (pred_alt, inv_y, y); } +libmvec_hidden_def (V_NAME_F1 (tan)) +HALF_WIDTH_ALIAS_F1 (tan) |