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| author | Ian Bolton <ian.bolton@arm.com> | 2014-04-24 07:15:33 +0100 |
|---|---|---|
| committer | Marcus Shawcroft <marcus.shawcroft@linaro.org> | 2014-04-24 07:15:33 +0100 |
| commit | e5e0d9a4f632735cf3bb440eecb5caee5eea44c1 (patch) | |
| tree | 51c5774783bb0479b35a33f9a22b86db00c20cbe /sysdeps/aarch64/fpu/feenablxcpt.c | |
| parent | bacc75f7be11656387c239831f490155f5fb3700 (diff) | |
| download | glibc-e5e0d9a4f632735cf3bb440eecb5caee5eea44c1.tar.gz glibc-e5e0d9a4f632735cf3bb440eecb5caee5eea44c1.tar.xz glibc-e5e0d9a4f632735cf3bb440eecb5caee5eea44c1.zip | |
[AArch64] Suppress unnecessary FPSR and FPCR writes.
Diffstat (limited to 'sysdeps/aarch64/fpu/feenablxcpt.c')
| -rw-r--r-- | sysdeps/aarch64/fpu/feenablxcpt.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/sysdeps/aarch64/fpu/feenablxcpt.c b/sysdeps/aarch64/fpu/feenablxcpt.c index 07a4bbb58e..70e413c9f6 100644 --- a/sysdeps/aarch64/fpu/feenablxcpt.c +++ b/sysdeps/aarch64/fpu/feenablxcpt.c @@ -23,6 +23,7 @@ int feenableexcept (int excepts) { fpu_control_t fpcr; + fpu_control_t fpcr_new; int original_excepts; _FPU_GETCW (fpcr); @@ -31,9 +32,10 @@ feenableexcept (int excepts) excepts &= FE_ALL_EXCEPT; - fpcr |= (excepts << FE_EXCEPT_SHIFT); + fpcr_new = fpcr | (excepts << FE_EXCEPT_SHIFT); - _FPU_SETCW (fpcr); + if (fpcr != fpcr_new) + _FPU_SETCW (fpcr_new); /* Trapping exceptions are optional in AArch64 the relevant enable bits in FPCR are RES0 hence the absence of support can be |