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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2024-09-23 15:30:20 +0100 |
|---|---|---|
| committer | Wilco Dijkstra <wilco.dijkstra@arm.com> | 2024-09-23 15:44:07 +0100 |
| commit | a15b1394b5eba98ffe28a02a392b587e4fe13c0d (patch) | |
| tree | d80072ec1d867aab9bd0e3060ff99b43588c7046 /sysdeps/aarch64/fpu/atan_advsimd.c | |
| parent | 7b8c134b5460ed933d610fa92ed1227372b68fdc (diff) | |
| download | glibc-a15b1394b5eba98ffe28a02a392b587e4fe13c0d.tar.gz glibc-a15b1394b5eba98ffe28a02a392b587e4fe13c0d.tar.xz glibc-a15b1394b5eba98ffe28a02a392b587e4fe13c0d.zip | |
AArch64: Improve codegen in SVE F32 logs
Reduce MOVPRFXs by using unpredicated (non-destructive) instructions where possible. Similar to the recent change to AdvSIMD F32 logs, adjust special-case arguments and bounds to allow for more optimal register usage. For all 3 routines one MOVPRFX remains in the reduction, which cannot be avoided as immediate AND and ASR are both destructive. Reviewed-by: Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Diffstat (limited to 'sysdeps/aarch64/fpu/atan_advsimd.c')
0 files changed, 0 insertions, 0 deletions