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author | Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com> | 2017-08-07 09:14:14 -0300 |
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committer | Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com> | 2017-08-10 16:10:21 -0300 |
commit | 4d98ace9de3183309cb394cd0110eda5ad2d2531 (patch) | |
tree | f6467c5c3fa12f02f563e3d5d126ec1a6658e903 /support/xpthread_mutexattr_setrobust.c | |
parent | 922369032c604b4dcfd535e1bcddd4687e7126a5 (diff) | |
download | glibc-4d98ace9de3183309cb394cd0110eda5ad2d2531.tar.gz glibc-4d98ace9de3183309cb394cd0110eda5ad2d2531.tar.xz glibc-4d98ace9de3183309cb394cd0110eda5ad2d2531.zip |
powerpc: Restrict xssqrtqp operands to Vector Registers (bug 21941)
POWER ISA 3.0 introduces the xssqrtqp instructions, which expects operands to be in Vector Registers (Altivec/VMX), even though this instruction belongs to the Vector-Scalar Instruction Set. In GCC's Extended Assembly for POWER, the 'wq' register constraint is provided for use with IEEE 754 128-bit floating-point values. However, this constraint does not limit the register allocation to Vector Registers (Altivec/VMX) and could assign a Vector-Scalar Register (VSX) to the operands of the instruction. This patch changes the register constraint used in sqrtf128 from 'wq' to 'v', in order to request a Vector Register (Altivec/VMX) for use with the xssqrtqp instruction. Tested for powerpc64le and --with-cpu=power9. [BZ #21941] * sysdeps/powerpc/fpu/math_private.h (__ieee754_sqrtf128): Since xssqrtqp requires operands to be in Vector Registers (Altivec/VMX), replace the register constraint 'wq' with 'v'. * sysdeps/powerpc/powerpc64le/power9/fpu/e_sqrtf128.c (__ieee754_sqrtf128): Likewise.
Diffstat (limited to 'support/xpthread_mutexattr_setrobust.c')
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