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author | Wilco Dijkstra <wdijkstr@arm.com> | 2020-07-15 16:55:07 +0100 |
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committer | Wilco Dijkstra <wdijkstr@arm.com> | 2020-07-15 16:55:07 +0100 |
commit | 4a733bf375238a6a595033b5785cea7f27d61307 (patch) | |
tree | e649148bc3df2bf6ce1d256b5d9c8dc6d70b4195 /signal/tst-sigwait-eintr.c | |
parent | 34f0d01d5e43c7dedd002ab47f6266dfb5b79c22 (diff) | |
download | glibc-4a733bf375238a6a595033b5785cea7f27d61307.tar.gz glibc-4a733bf375238a6a595033b5785cea7f27d61307.tar.xz glibc-4a733bf375238a6a595033b5785cea7f27d61307.zip |
AArch64: Add optimized Q-register memcpy
Add a new memcpy using 128-bit Q registers - this is faster on modern cores and reduces codesize. Similar to the generic memcpy, small cases include copies up to 32 bytes. 64-128 byte copies are split into two cases to improve performance of 64-96 byte copies. Large copies align the source rather than the destination. bench-memcpy-random is ~9% faster than memcpy_falkor on Neoverse N1, so make this memcpy the default on N1 (on Centriq it is 15% faster than memcpy_falkor). Passes GLIBC regression tests. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'signal/tst-sigwait-eintr.c')
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