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author | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:26:40 +0000 |
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committer | Joseph Myers <joseph@codesourcery.com> | 2013-06-05 20:26:40 +0000 |
commit | 5556231db2301917cd14a7450de4eba2368c9763 (patch) | |
tree | 2456b4a2ec7e4377c420b2f94285dddb53784e5f /ports/sysdeps/alpha/memchr.c | |
parent | 869378a5bf1d415f52c14d9697b886d8143a73e1 (diff) | |
download | glibc-5556231db2301917cd14a7450de4eba2368c9763.tar.gz glibc-5556231db2301917cd14a7450de4eba2368c9763.tar.xz glibc-5556231db2301917cd14a7450de4eba2368c9763.zip |
Remove trailing whitespace in ports.
Diffstat (limited to 'ports/sysdeps/alpha/memchr.c')
-rw-r--r-- | ports/sysdeps/alpha/memchr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ports/sysdeps/alpha/memchr.c b/ports/sysdeps/alpha/memchr.c index 67f718a50e..4f634cef7a 100644 --- a/ports/sysdeps/alpha/memchr.c +++ b/ports/sysdeps/alpha/memchr.c @@ -115,7 +115,7 @@ __memchr (const void *s, int xc, size_t n) s_align++; \ n -= 64; \ } while (0) - + /* While there's still lots more data to potentially be read, continue issuing prefetches for the 4th cacheline out. */ while (n >= 256) |