diff options
| author | Paul Clarke <pc@us.ibm.com> | 2017-06-09 14:36:22 -0300 |
|---|---|---|
| committer | Tulio Magno Quites Machado Filho <tuliom@linux.vnet.ibm.com> | 2017-06-09 14:36:22 -0300 |
| commit | cdfbe5037f2f67bf5f560b73732b69d0fabe2314 (patch) | |
| tree | 67f2fd18a8718ef1e19b134e218c4a90fdffd067 /nptl/tst-tls5.h | |
| parent | d6bd839b9acfe619afa1db67a2882c0ce839861f (diff) | |
| download | glibc-cdfbe5037f2f67bf5f560b73732b69d0fabe2314.tar.gz glibc-cdfbe5037f2f67bf5f560b73732b69d0fabe2314.tar.xz glibc-cdfbe5037f2f67bf5f560b73732b69d0fabe2314.zip | |
powerpc: add sysconf support for cache geometries
There is currently no "cross-platform" (x86 and POWER) support for determining the cacheline size. This patch adds support to sysconf() to correctly report cacheline sizes based on the information in the auxilliary vector. Thus, using sysconf() is a cross-platform (x86 and POWER) solution for determining cacheline sizes. Support is added (on powerpc) for: _SC_LEVEL1_ICACHE_SIZE _SC_LEVEL1_ICACHE_ASSOC _SC_LEVEL1_ICACHE_LINESIZE _SC_LEVEL1_DCACHE_SIZE _SC_LEVEL1_DCACHE_ASSOC _SC_LEVEL1_DCACHE_LINESIZE _SC_LEVEL2_CACHE_SIZE _SC_LEVEL2_CACHE_ASSOC _SC_LEVEL2_CACHE_LINESIZE _SC_LEVEL3_CACHE_SIZE _SC_LEVEL3_CACHE_ASSOC _SC_LEVEL3_CACHE_LINESIZE * sysdeps/unix/sysv/linux/powerpc/sysconf.c: New file. Add powerpc-specific overrides for L1, L2, L3 CACHE_SIZEs, CACHE_ASSOCs, and CACHE_LINESIZEs, retrieving from auxv. * sysdeps/unix/sysv/linux/powerpc/test-powerpc-linux-sysconf.c: New file. Invoke newly supported sysconf values for powerpc, and report results. If none are supported, report so. * sysdeps/unix/sysv/linux/powerpc/Makefile (tests): Add new test, tst-sysconf.
Diffstat (limited to 'nptl/tst-tls5.h')
0 files changed, 0 insertions, 0 deletions