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| author | Sajan Karumanchi <sajan.karumanchi@amd.com> | 2020-10-28 13:05:33 +0530 |
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| committer | Florian Weimer <fweimer@redhat.com> | 2020-10-28 09:57:14 +0100 |
| commit | 59803e81f96b479c17f583b31eac44b57591a1bf (patch) | |
| tree | a580e2fd555e4d83fb095b2f2523cb180e5df4c1 /nptl/tst-rwlock-pwn.c | |
| parent | 641a12484562b3a740b940620ac2c47a626c9861 (diff) | |
| download | glibc-59803e81f96b479c17f583b31eac44b57591a1bf.tar.gz glibc-59803e81f96b479c17f583b31eac44b57591a1bf.tar.xz glibc-59803e81f96b479c17f583b31eac44b57591a1bf.zip | |
x86: Optimizing memcpy for AMD Zen architecture.
Modifying the shareable cache '__x86_shared_cache_size', which is a factor in computing the non-temporal threshold parameter '__x86_shared_non_temporal_threshold' to optimize memcpy for AMD Zen architectures. In the existing implementation, the shareable cache is computed as 'L3 per thread, L2 per core'. Recomputing this shareable cache as 'L3 per CCX(Core-Complex)' has brought in performance gains. As per the large bench variant results, this patch also addresses the regression problem on AMD Zen architectures. Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
Diffstat (limited to 'nptl/tst-rwlock-pwn.c')
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