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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-10-04 10:38:57 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-10-05 16:54:16 +0100 |
| commit | 5a4b6f8e4b7e2a76c71b713200a80181d745c93d (patch) | |
| tree | 4d5e092d4e36c23497c9174531394c89342d32c4 /nis | |
| parent | 480a0dfe1acab3dbf1bdcfa37fdca992eb9c54a5 (diff) | |
| download | glibc-5a4b6f8e4b7e2a76c71b713200a80181d745c93d.tar.gz glibc-5a4b6f8e4b7e2a76c71b713200a80181d745c93d.tar.xz glibc-5a4b6f8e4b7e2a76c71b713200a80181d745c93d.zip | |
aarch64: Optimise vecmath logs
* Transpose table layout for improved memory access
* Use half-vector special comparisons for AdvSIMD
* Improve register use near special-case branches
- Due to the presence of a function call, return value would get
mov-d out of x0 in order to facilitate PCS. By moving the final
computation after the branch this can be avoided
Also change SVE routines to use overloaded intrinsics for readability.
Diffstat (limited to 'nis')
0 files changed, 0 insertions, 0 deletions