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authorAdhemerval Zanella <adhemerval.zanella@linaro.org>2021-06-22 16:41:28 -0300
committerAdhemerval Zanella <adhemerval.zanella@linaro.org>2021-06-24 09:57:46 -0300
commite3e3eb0a2ea615c272cec5f47ba9f243ccdaf386 (patch)
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parentea26ff03227d7cacef5de6036df57734373449b4 (diff)
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x86: Fix tst-cpu-features-cpuinfo on Ryzen 9 (BZ #27873)
AMD define different flags for IRPB, IBRS, and STIPBP [1], so new
x86_64_cpu are added and IBRS_IBPB is only tested for Intel.

The SSDB is also defined and implemented different on AMD [2],
and also a new AMD_SSDB flag is added.  It should map to the
cpuinfo 'ssdb' on recent AMD cpus.

It fixes tst-cpu-features-cpuinfo and tst-cpu-features-cpuinfo-static
on recent AMD cpus.

Checked on x86_64-linux-gnu on AMD Ryzen 9 5900X.

[1] https://developer.amd.com/wp-content/resources/Architecture_Guidelines_Update_Indirect_Branch_Control.pdf
[2] https://bugzilla.kernel.org/show_bug.cgi?id=199889

Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
Diffstat (limited to 'manual/platform.texi')
-rw-r--r--manual/platform.texi12
1 files changed, 12 insertions, 0 deletions
diff --git a/manual/platform.texi b/manual/platform.texi
index a0b204b099..4cd029cfad 100644
--- a/manual/platform.texi
+++ b/manual/platform.texi
@@ -178,6 +178,18 @@ The supported processor features are:
 @code{AESKLE} -- AES Key Locker instructions are enabled by OS.
 
 @item
+@code{AMD_IBPB} -- Indirect branch predictor barrier (IBPB) for AMD cpus.
+
+@item
+@code{AMD_IBRS} -- Indirect branch restricted speculation (IBPB) for AMD cpus.
+
+@item
+@code{AMD_SSBD} -- Speculative Store Bypass Disable (SSBD) for AMD cpus.
+
+@item
+@code{AMD_STIBP} -- Single thread indirect branch predictors (STIBP) for AMD cpus.
+
+@item
 @code{AMX_BF16} -- Tile computational operations on bfloat16 numbers.
 
 @item