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author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-01-03 15:36:53 -0200 |
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committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2018-01-04 17:49:17 -0200 |
commit | 4854ddd874d4aafb1ac21f551abda58ac4f9144d (patch) | |
tree | 3151c3e8a5dba998e870afadbdd59bc07bf36e6a /libof-iterator.mk | |
parent | 8a5df95ffa83f525a4f638ead743f4fa2b7fe45a (diff) | |
download | glibc-4854ddd874d4aafb1ac21f551abda58ac4f9144d.tar.gz glibc-4854ddd874d4aafb1ac21f551abda58ac4f9144d.tar.xz glibc-4854ddd874d4aafb1ac21f551abda58ac4f9144d.zip |
alpha: Remove s_ceil{f} and s_floor{f} implementation (BZ#22665)
As discussed in libc-alpha [1], alpha ceil{f} and floor{f} implementation uses cvttq/svm and although the Alpha Architecture Handbook version 3 states that that CVTfi OUTPUT Exceptions (B.3 Mapping to IEEE Standard) should not generate Inexact if INE bit is set on fpcr, the Alpha 21264 [1] chip manual (A.8 IEEE Floating-Point Conformance) states that CVTfi and CVTif OUTPUT does generate inexact exception for inexact result regardless. As Joseph noted [2] to correctly fix it on alpha we need to either avoid the instruction or avoid any inexact bit from it being set on return from the function (while preserving the inexact bit that might be set on the entry to the function). The later will result mf_fpcr followed by a mt_fpcr to get and set the fpcr which will defeat the optimization itself. So the patch just remove the alpha optimized and rely on generic implementation. It fixes the math/test-*-{ceil,floor} on alpha. [BZ #15479] [BZ #22665] * sysdeps/alpha/fpu/s_ceil.c: Remove file. * sysdeps/alpha/fpu/s_ceilf.c: Likewise. * sysdeps/alpha/fpu/s_floor.c: Likewise. * sysdeps/alpha/fpu/s_floorf.c: Likewise. [1] https://www.star.bnl.gov/public/daq/HARDWARE/21264_data_sheet.pdf [2] https://sourceware.org/ml/libc-alpha/2018-01/msg00086.html Signed-off-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
Diffstat (limited to 'libof-iterator.mk')
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