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| author | Ryan S. Arnold <rsa@linux.vnet.ibm.com> | 2012-10-30 17:07:18 -0500 |
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| committer | Ryan S. Arnold <rsa@linux.vnet.ibm.com> | 2012-10-30 17:07:18 -0500 |
| commit | 09dec6c37e3cd967f62795320703647f24545e3e (patch) | |
| tree | 78b5597c0aa457682a6215382022348ec87d07c5 /elf/tst-tlsmod2.c | |
| parent | 9f45bfe790a59bfc072ef096b21dc701e03bccf9 (diff) | |
| download | glibc-09dec6c37e3cd967f62795320703647f24545e3e.tar.gz glibc-09dec6c37e3cd967f62795320703647f24545e3e.tar.xz glibc-09dec6c37e3cd967f62795320703647f24545e3e.zip | |
Correct cacheline size to 32-bytes for ppc405 memset.S (bug 14595).
This patch also creates a version of memset.S for the ppc476 processor which uses a 128-byte cacheline size for dcbz insns.
Diffstat (limited to 'elf/tst-tlsmod2.c')
0 files changed, 0 insertions, 0 deletions