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| author | Andrew Senkevich <andrew.senkevich@intel.com> | 2016-12-19 13:20:31 +0300 |
|---|---|---|
| committer | Andrew Senkevich <andrew.senkevich@intel.com> | 2016-12-19 14:15:57 +0300 |
| commit | 2702856bf45c82cf8e69f2064f5aa15c0ceb6359 (patch) | |
| tree | e40c77e7ecb5974aedb1ba173bc52d1aa183898f /benchtests/bench-strrchr.c | |
| parent | 7051390094c124e4b98e6c57a8b47890b212c299 (diff) | |
| download | glibc-2702856bf45c82cf8e69f2064f5aa15c0ceb6359.tar.gz glibc-2702856bf45c82cf8e69f2064f5aa15c0ceb6359.tar.xz glibc-2702856bf45c82cf8e69f2064f5aa15c0ceb6359.zip | |
Disable TSX on some Haswell processors.
Patch disables Intel TSX on some Haswell processors to avoid TSX
on kernels that weren't updated with the latest microcode package
(which disables broken feature by default).
* sysdeps/x86/cpu-features.c (get_common_indeces): Add
stepping identification.
(init_cpu_features): Add handle of Haswell.
Diffstat (limited to 'benchtests/bench-strrchr.c')
0 files changed, 0 insertions, 0 deletions