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| author | Paul A. Clarke <pc@us.ibm.com> | 2019-09-19 11:39:44 -0500 |
|---|---|---|
| committer | Paul A. Clarke <pc@us.ibm.com> | 2019-09-27 08:53:01 -0500 |
| commit | e68b1151f7460d5fa88c3a567c13f66052da79a7 (patch) | |
| tree | 5ad422da01176650d27386a6901ca53c5630b2b8 /ChangeLog | |
| parent | 7413c188c77adb26a15cf0e98e0a991d09d73c65 (diff) | |
| download | glibc-e68b1151f7460d5fa88c3a567c13f66052da79a7.tar.gz glibc-e68b1151f7460d5fa88c3a567c13f66052da79a7.tar.xz glibc-e68b1151f7460d5fa88c3a567c13f66052da79a7.zip | |
[powerpc] __fesetround_inline optimizations
On POWER9, use more efficient means to update the 2-bit rounding mode via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions or one 'mtfsfi' instruction that modifies 4 bits). Suggested-by: Paul E. Murphy <murphyp@linux.ibm.com> Reviewed-By: Paul E Murphy <murphyp@linux.ibm.com>
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index c27d1433fa..a1192a3a70 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,11 @@ 2019-09-27 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use + 'mffscrn' instruction on POWER9. + (__fesetround_inline_nocheck): Likewise. + +2019-09-27 Paul A. Clarke <pc@us.ibm.com> + * sysdeps/powerpc/fpu/fenv_libc.h (FPSCR_EXCEPTIONS_MASK): New. * sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Optimize to write FPSCR control only, if exceptions have not changed. |