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| author | H.J. Lu <hjl.tools@gmail.com> | 2016-05-19 09:09:00 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2016-05-19 09:09:00 -0700 |
| commit | 7c08d791ee4fabf96d96b66dec803602e621057c (patch) | |
| tree | fdc67fe76da8482d407594c70260a64c27e31cb7 /ChangeLog | |
| parent | eb2c88c7c83901737db5c4de7dc4470c5681b2cb (diff) | |
| download | glibc-7c08d791ee4fabf96d96b66dec803602e621057c.tar.gz glibc-7c08d791ee4fabf96d96b66dec803602e621057c.tar.xz glibc-7c08d791ee4fabf96d96b66dec803602e621057c.zip | |
Check the HTT bit before counting logical threads
Skip counting logical threads for Intel processors if the HTT bit is 0 which indicates there is only a single logical processor. * sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting logical threads if the HTT bit is 0. * sysdeps/x86/cpu-features.h (bit_cpu_HTT): New. (index_cpu_HTT): Likewise. (reg_HTT): Likewise.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 8a4918cbc8..8adf828d1b 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,13 @@ 2016-05-19 H.J. Lu <hongjiu.lu@intel.com> + * sysdeps/x86/cacheinfo.c (init_cacheinfo): Skip counting + logical threads if the HTT bit is 0. + * sysdeps/x86/cpu-features.h (bit_cpu_HTT): New. + (index_cpu_HTT): Likewise. + (reg_HTT): Likewise. + +2016-05-19 H.J. Lu <hongjiu.lu@intel.com> + [BZ #20115] * sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S (__memset): Remove alignments on jump targets. |