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| author | Kaz Kojima <kkojima@rr.iij4u.or.jp> | 2012-04-05 11:57:03 +0900 |
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| committer | Kaz Kojima <kkojima@rr.iij4u.or.jp> | 2012-04-05 11:57:03 +0900 |
| commit | 2ecccfc97ac9e755f6b67fa0bac785148c7b8256 (patch) | |
| tree | 00b574fa18c2b9af6399c6c4dc0e6109402177d2 /ChangeLog | |
| parent | 8a53f50f2a8ab4e1166afa0e9a8d4abc62b0ed4e (diff) | |
| download | glibc-2ecccfc97ac9e755f6b67fa0bac785148c7b8256.tar.gz glibc-2ecccfc97ac9e755f6b67fa0bac785148c7b8256.tar.xz glibc-2ecccfc97ac9e755f6b67fa0bac785148c7b8256.zip | |
Set SH fpcsr register which read again.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 092756e6f7..9c9947984f 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,11 @@ 2012-04-05 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * sysdeps/sh/sh4/fpu/fegetenv.c (fegetenv): Set fpscr register which + read again. + * sysdeps/sh/sh4/fpu/ftestexcept.c: Likewise. + +2012-04-05 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> + * sysdeps/sh/sh4/fpu/fraiseexcpt.c (feraiseexcept): Produce an exception using FPU order intentionally. |