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| author | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2024-05-07 09:19:48 -0300 |
|---|---|---|
| committer | Adhemerval Zanella <adhemerval.zanella@linaro.org> | 2024-05-09 08:59:30 -0300 |
| commit | ae515ba530be76d6627740ddc33a3a63f8c7e4f9 (patch) | |
| tree | 75fbf70a9b772ce5b0ad97db0f02d3b205789e1e | |
| parent | dd5f891c1ad9f1b43b9db93afe2a55cbb7a6194e (diff) | |
| download | glibc-ae515ba530be76d6627740ddc33a3a63f8c7e4f9.tar.gz glibc-ae515ba530be76d6627740ddc33a3a63f8c7e4f9.tar.xz glibc-ae515ba530be76d6627740ddc33a3a63f8c7e4f9.zip | |
powerpc: Fix __fesetround_inline_nocheck on POWER9+ (BZ 31682)
The e68b1151f7460d5fa88c3a567c13f66052da79a7 commit changed the __fesetround_inline_nocheck implementation to use mffscrni (through __fe_mffscrn) instead of mtfsfi. For generic powerpc ceil/floor/trunc, the function is supposed to disable the floating-point inexact exception enable bit, however mffscrni does not change any exception enable bits. This patch fixes by reverting the optimization for the __fesetround_inline_nocheck. Checked on powerpc-linux-gnu. Reviewed-by: Paul E. Murphy <murphyp@linux.ibm.com>
| -rw-r--r-- | sysdeps/powerpc/fpu/fenv_libc.h | 16 | ||||
| -rw-r--r-- | sysdeps/powerpc/fpu/round_to_integer.h | 6 |
2 files changed, 8 insertions, 14 deletions
diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index f9167056a8..0a06e4486b 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -182,19 +182,13 @@ __fesetround_inline (int round) return 0; } -/* Same as __fesetround_inline, however without runtime check to use DFP - mtfsfi syntax (as relax_fenv_state) or if round value is valid. */ +/* Same as __fesetround_inline, and it also disable the floating-point + inexact execption (bit 60 - XE, assuming NI is 0). It does not check + if ROUND is a valid value. */ static inline void -__fesetround_inline_nocheck (const int round) +__fesetround_inline_disable_inexact (const int round) { -#ifdef _ARCH_PWR9 - __fe_mffscrn (round); -#else - if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) - __fe_mffscrn (round); - else - asm volatile ("mtfsfi 7,%0" : : "n" (round)); -#endif + asm volatile ("mtfsfi 7,%0" : : "n" (round)); } #define FPSCR_MASK(bit) (1 << (31 - (bit))) diff --git a/sysdeps/powerpc/fpu/round_to_integer.h b/sysdeps/powerpc/fpu/round_to_integer.h index b68833640f..6996519c61 100644 --- a/sysdeps/powerpc/fpu/round_to_integer.h +++ b/sysdeps/powerpc/fpu/round_to_integer.h @@ -42,14 +42,14 @@ set_fenv_mode (enum round_mode mode) switch (mode) { case CEIL: - __fesetround_inline_nocheck (FE_UPWARD); + __fesetround_inline_disable_inexact (FE_UPWARD); break; case FLOOR: - __fesetround_inline_nocheck (FE_DOWNWARD); + __fesetround_inline_disable_inexact (FE_DOWNWARD); break; case TRUNC: case ROUND: - __fesetround_inline_nocheck (FE_TOWARDZERO); + __fesetround_inline_disable_inexact (FE_TOWARDZERO); break; case NEARBYINT: /* Disable FE_INEXACT exception */ |