about summary refs log tree commit diff
diff options
context:
space:
mode:
authorH.J. Lu <hjl.tools@gmail.com>2013-07-02 08:03:29 -0700
committerH.J. Lu <hjl.tools@gmail.com>2013-07-02 08:06:04 -0700
commit1c81621c5bbecb223c9d1262c05175608c47add5 (patch)
treebbfd0f4a2731c6ace22cb3d66887081845b8a342
parent77f01ab5d1d2eead1bd4a9135d6a76ebd3fe21e5 (diff)
downloadglibc-1c81621c5bbecb223c9d1262c05175608c47add5.tar.gz
glibc-1c81621c5bbecb223c9d1262c05175608c47add5.tar.xz
glibc-1c81621c5bbecb223c9d1262c05175608c47add5.zip
Enable static 32-bit SSE4.2 strcasecmp/strncasecmp
-rw-r--r--ChangeLog6
-rw-r--r--sysdeps/i386/i686/multiarch/strcasecmp.S3
-rw-r--r--sysdeps/i386/i686/multiarch/strncase.S3
3 files changed, 6 insertions, 6 deletions
diff --git a/ChangeLog b/ChangeLog
index 4a2d19ad03..0b37552bd5 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2013-07-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* sysdeps/i386/i686/multiarch/strcasecmp.S (__strcasecmp): Enable
+	SSE4.2 strcasecmp for libc.a.
+	* sysdeps/i386/i686/multiarch/strncase.S (__strncasecmp): Likewise.
+
 2013-07-02  Joseph Myers  <joseph@codesourcery.com>
 
 	[BZ #13304]
diff --git a/sysdeps/i386/i686/multiarch/strcasecmp.S b/sysdeps/i386/i686/multiarch/strcasecmp.S
index 3b38214c9b..2444af26c3 100644
--- a/sysdeps/i386/i686/multiarch/strcasecmp.S
+++ b/sysdeps/i386/i686/multiarch/strcasecmp.S
@@ -54,12 +54,9 @@ ENTRY(__strcasecmp)
 	testl	$bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features
 	jz	2f
 	leal	__strcasecmp_ssse3, %eax
-#if 0
-	// XXX Temporarily
 	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	__strcasecmp_sse4_2, %eax
-#endif
 2:	ret
 END(__strcasecmp)
 #endif
diff --git a/sysdeps/i386/i686/multiarch/strncase.S b/sysdeps/i386/i686/multiarch/strncase.S
index 51c6d721c9..939cd96ce0 100644
--- a/sysdeps/i386/i686/multiarch/strncase.S
+++ b/sysdeps/i386/i686/multiarch/strncase.S
@@ -54,12 +54,9 @@ ENTRY(__strncasecmp)
 	testl	$bit_SSSE3, CPUID_OFFSET+index_SSSE3+__cpu_features
 	jz	2f
 	leal	__strncasecmp_ssse3, %eax
-#if 0
-	// XXX Temporarily
 	testl	$bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features
 	jz	2f
 	leal	__strncasecmp_sse4_2, %eax
-#endif
 2:	ret
 END(__strncasecmp)
 #endif