arch/mips/atomic_arch.h


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

#define a_ll a_ll
static inline int a_ll(volatile int *p)
{
	int v;
	__asm__ __volatile__ (
		".set push ; .set mips2\n\t"
		"ll %0, %1"
		"\n\t.set pop"
		: "=r"(v) : "m"(*p));
	return v;
}

#define a_sc a_sc
static inline int a_sc(volatile int *p, int v)
{
	int r;
	__asm__ __volatile__ (
		".set push ; .set mips2\n\t"
		"sc %0, %1"
		"\n\t.set pop"
		: "=r"(r), "=m"(*p) : "0"(v) : "memory");
	return r;
}

#define a_barrier a_barrier
static inline void a_barrier()
{
	/* mips2 sync, but using too many directives causes
	 * gcc not to inline it, so encode with .long instead. */
	__asm__ __volatile__ (".long 0xf" : : : "memory");
#if 0
	__asm__ __volatile__ (
		".set push ; .set mips2 ; sync ; .set pop"
		: : : "memory");
#endif
}

#define a_pre_llsc a_barrier
#define a_post_llsc a_barrier