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* aarch64: add HWCAP_ definitions from linux v5.0Szabolcs Nagy2019-03-131-0/+3
| | | | | | | | HWCAP_SB - speculation barrier instruction available added in linux commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d HWCAP_PACA, HWCAP_PACG - pointer authentication instructions available (address and generic) added in linux commit 7503197562567b57ec14feb3a9d5400ebc56812f
* aarch64, or1k: add kexec_file_load syscall number from linux v5.0Szabolcs Nagy2019-03-132-0/+2
| | | | added in linux commit 4e21565b7fd4d9045765f697887e74a704135fe2
* powerpc: add PTRACE_SYSEMU from linux v4.20Szabolcs Nagy2019-03-132-0/+4
| | | | added in linux commit 5521eb4bca2db733952f068c37bdf3cd656ad23c
* aarch64: add HWCAP_SSBS from linux v4.20Szabolcs Nagy2019-03-131-0/+1
| | | | | for armv8.5 speculative store bypass PSTATE bit support, added in linux commit d71be2b6c0e19180b5f80a6d42039cc074a693a2
* bits/ioctl.h: add TIOC{G,S}ISO7816 from linux v4.20Szabolcs Nagy2019-03-131-0/+2
| | | | | | | | | | | | | | | | | | | | | ISO7816 smart cards ioctls. linux commit ad8c0eaa0a418ae8ef3f9217638bb86439399eac the actual kernel definitions are #define TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) #define TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) where struct serial_iso7816 is defined in linux/serial.h as struct serial_iso7816 { __u32 flags; __u32 tg; __u32 sc_fi; __u32 sc_di; __u32 clk; __u32 reserved[5]; };
* arm: add io_pgetevents syscall number from v4.19Szabolcs Nagy2019-03-131-0/+1
| | | | wired up in linux commit 73aeb2cbcdc9be391b3d32a55319a59ce425426f
* aarch64, or1k: define rseq syscall number following linux v4.19Szabolcs Nagy2019-03-132-0/+2
| | | | added in linux commit db7a2d1809a5b6b08d138ff68837f805fc073351
* fix POSIX_FADV_DONTNEED/_NOREUSE on s390xJonathan Neuschäfer2019-03-131-0/+3
| | | | | | | | | On s390x, POSIX_FADV_DONTNEED and POSIX_FADV_NOREUSE have different values than on all other architectures that Linux supports. Handle this difference by wrapping their definitions in include/fcntl.h in #ifdef, so that arch/s390x/bits/fcntl.h can override them.
* move arch-invariant definitions out of bits/ioctl.hBobby Bingham2019-02-077-682/+0
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* add io_pgetevents and rseq syscall numbers from linux v4.18Szabolcs Nagy2018-12-0913-0/+23
| | | | | | | | io_pgetevents is new in linux commit 7a074e96dee62586c935c80cecd931431bfdd0be rseq is new in linux commit d7822b1e24f2df5df98c76f0e94a5416349ff759
* make thread-pointer-loading asm non-volatileRich Felker2018-10-1614-19/+19
| | | | | | | | | | this will allow the compiler to cache and reuse the result, meaning we no longer have to take care not to load it more than once for the sake of archs where the load may be expensive. depends on commit 1c84c99913bf1cd47b866ed31e665848a0da84a2 for correctness, since otherwise the compiler could hoist loads during stage 3 of dynamic linking before the initial thread-pointer setup.
* remove ancient clang workaround from powerpc pthread_arch.h asmRich Felker2018-10-161-5/+0
| | | | | versions of clang all the way back to 3.1 lack the bug this was purportedly working around.
* add TLSDESC support for 32-bit armRich Felker2018-10-011-1/+3
| | | | | | | | | | | | | | | unlike other asm where the baseline ISA is used, these functions are hot paths and use ISA-level specializations. call-clobbered vfp registers are saved before calling __tls_get_new, since there is no guarantee it won't use them. while setjmp/longjmp have to use hwcap to decide whether to the fpu is in use, since application code could be using vfp registers even if libc was compiled as pure softfloat, __tls_get_new is part of libc and can be assumed not to have access to vfp registers if tlsdesc.S does not. thus it suffices just to check the predefined preprocessor macros. the check for __ARM_PCS_VFP is redundant; !__SOFTFP__ must always be true if the target ISA level includes fpu instructions/registers.
* add arm and sh bits/ptrace.hSzabolcs Nagy2018-09-202-0/+30
| | | | | | These should have been added in commit df6d9450ea19fd71e52cf5cdb4c85beb73066394 that added target specific PTRACE_ macros, but somehow got missed.
* fix broken atomic store on powerpc[64]Rich Felker2018-09-142-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | in our memory model, all atomics are supposed to be full barriers; stores are not release-only. this is important because store is used as an unlock operation in places where it needs to acquire the waiter count to determine if a futex wake is needed. at least in the malloc-internal locks, but possibly elsewhere, soft deadlocks from missing futex wake (breakable by poking the threads to restart the syscall, e.g. by attaching a tracer) were reported to occur. once the malloc lock is replaced with Jens Gustedt's new lock implementation (see commit 47d0bcd4762f223364e5b58d5a381aaa0cbd7c38), malloc will not be affected by the issue, but it's not clear that other uses won't be. reducing the strength of the ordering properties required from a_store would require a thorough analysis of how it's used. to fix the problem, I'm removing the powerpc[64]-specific a_store definition; now, the top-level atomic.h will implement a_store using a_barrier on both sides of the store. it's not clear to me yet whether there might be issues with the other atomics. it's possible that a_post_llsc needs to be replaced with a full barrier to guarantee the formal semanics we want, but either way I think the difference is unlikely to impact the way we use them.
* apply hidden visibility to sigreturn code fragmentsRich Felker2018-09-126-6/+18
| | | | | | | these were overlooked in the declarations overhaul work because they are not properly declared, and the current framework even allows their declared types to vary by arch. at some point this should be cleaned up, but I'm not sure what the right way would be.
* define and use internal macros for hidden visibility, weak refsRich Felker2018-09-055-8/+9
| | | | | | | | | this cleans up what had become widespread direct inline use of "GNU C" style attributes directly in the source, and lowers the barrier to increased use of hidden visibility, which will be useful to recovering some of the efficiency lost when the protected visibility hack was dropped in commit dc2f368e565c37728b0d620380b849c3a1ddd78f, especially on archs where the PLT ABI is costly.
* fix async thread cancellation on sh-fdpicRich Felker2018-08-291-0/+5
| | | | | | | | | | | | | | if __cp_cancel was reached via __syscall_cp, r12 will necessarily still contain a GOT pointer (for libc.so or for the static-linked main program) valid for entering __cancel. however, in the case of async cancellation, r12 may contain any scratch value; it's not necessarily even a valid GOT pointer for the code that was interrupted. unlike in commit 0ec49dab6794166d67fae4764ce7fdea42ea6103 where the corresponding issue was fixed for powerpc64, there is fundamentally no way for fdpic code to recompute its GOT pointer. so a new mechanism is introduced for cancel_handler to write a GOT register value into the interrupted context on archs where it is needed.
* move inclusion of linux headers for kd.h, soundcard.h, vt.h to bitsmidipix2018-07-203-0/+3
| | | | | | | | | | | | maintainer's note: while musl does not use the linux kernel headers, it does provide these three sys/* headers which do nothing but include the corresponding linux/* headers, since the sys/* versions are the ones documented for application use (and they arguably provide interfaces that are not linux-specific but common to other unices). these headers should probably not be provided by libc (rather by a separate package), but as long as they are, use the bits header framework as an aid to out-of-tree ports of musl for non-linux systems that want to implement them in some other way.
* add support for arch-specific ptrace command macrosSzabolcs Nagy2018-07-1711-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | sys/ptrace.h is target specific, use bits/ptrace.h to add target specific macro definitions. these macros are kept in the generic sys/ptrace.h even though some targets don't support them: PTRACE_GETREGS PTRACE_SETREGS PTRACE_GETFPREGS PTRACE_SETFPREGS PTRACE_GETFPXREGS PTRACE_SETFPXREGS so no macro definition got removed in this patch on any target. only s390x has a numerically conflicting macro definition (PTRACE_SINGLEBLOCK). the PT_ aliases follow glibc headers, otherwise the definitions come from linux uapi headers except ones that are skipped in glibc and there is no real kernel support (s390x PTRACE_*_AREA) or need special type definitions (mips PTRACE_*_WATCH_*) or only relevant for linux 2.4 compatibility (PTRACE_OLDSETOPTIONS).
* fix regression in powerpc[64] SO_PEERSEC definitionRich Felker2018-06-262-0/+2
| | | | | | | commit 587f5a53bc3a68d80b239ba515d583df690a96df moved the definition of SO_PEERSEC to bits/socket.h for archs where the SO_* macros differ from their standard values, but failed to add copies of the generic definition for powerpc and powerpc64.
* fix value of SO_PEERSEC on mips archsRich Felker2018-06-263-0/+3
| | | | adapted from patch by Matthias Schiffer.
* add m68k reg.h and user.hRich Felker2018-06-262-0/+78
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* fix m68k float.h long double exponent rangeRich Felker2018-06-201-2/+2
| | | | | unlike the x86 variant, the m68k ld80 format allows (biased) exponent zero with mantissa msb set, thereby extending the normal range.
* work around broken kernel struct ipc_perm on some big endian archsRich Felker2018-06-204-0/+7
| | | | | | | | | | | | | | | the mode member of struct ipc_perm is specified by POSIX to have type mode_t, which is uniformly defined as unsigned int. however, Linux defines it with type __kernel_mode_t, and defines __kernel_mode_t as unsigned short on some archs. since there is a subsequent padding field, treating it as a 32-bit unsigned int works on little endian archs, but the order is backwards on big endian archs with the erroneous definition. since multiple archs are affected, remedy the situation with fixup code in the affected functions (shmctl, semctl, and msgctl) rather than repeating the same shims in syscall_arch.h for every affected arch.
* s390x: add kexec_file_load syscall number from linux v4.17Szabolcs Nagy2018-06-191-0/+1
| | | | new in linux commit 71406883fd35794d573b3085433c41d0a3bf6c21
* mips: add HWCAP_ flags from linux v4.17Szabolcs Nagy2018-06-193-0/+3
| | | | new in linux commit 256211f2b0b251e532d1899b115e374feb16fa7a
* aarch64: add HWCAP_ flags from linux v4.17Szabolcs Nagy2018-06-191-0/+4
| | | | | hwcaps for armv8.4, new in linux commit 7206dc93a58fb76421c4411eefa3c003337bcb2d
* powerpc: add pkey syscall numbers from linux v4.16Szabolcs Nagy2018-06-192-0/+6
| | | | | | add pkey_mprotect, pkey_alloc, pkey_free syscall numbers, new in linux commits 3350eb2ea127978319ced883523d828046af4045 and 9499ec1b5e82321829e1c1510bcc37edc20b6f38
* aarch64: add HWCAP_ASIMDFHM from linux v4.16Szabolcs Nagy2018-06-191-0/+1
| | | | | armv8.4 fp mul instructions. added in commit 3b3b681097fae73b7f5dcdd42db6cfdf32943d4c
* add m68k portRich Felker2018-06-1917-0/+847
| | | | | | | | | | | | | three ABIs are supported: the default with 68881 80-bit fpu format and results returned in floating point registers, softfloat-only with the same format, and coldfire fpu with IEEE single/double only. only the first is tested at all, and only under qemu which has fpu emulation bugs. basic functionality smoke tests have been performed for the most common arch-specific breakage via libc-test and qemu user-level emulation. some sysvipc failures remain, but are shared with other big endian archs and will be fixed separately.
* fix TLS layout of TLS variant I when there is a gap above TPSzabolcs Nagy2018-06-0212-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | In TLS variant I the TLS is above TP (or above a fixed offset from TP) but on some targets there is a reserved gap above TP before TLS starts. This matters for the local-exec tls access model when the offsets of TLS variables from the TP are hard coded by the linker into the executable, so the libc must compute these offsets the same way as the linker. The tls offset of the main module has to be alignup(GAP_ABOVE_TP, main_tls_align). If there is no TLS in the main module then the gap can be ignored since musl does not use it and the tls access models of shared libraries are not affected. The previous setup only worked if (tls_align & -GAP_ABOVE_TP) == 0 (i.e. TLS did not require large alignment) because the gap was treated as a fixed offset from TP. Now the TP points at the end of the pthread struct (which is aligned) and there is a gap above it (which may also need alignment). The fix required changing TP_ADJ and __pthread_self on affected targets (aarch64, arm and sh) and in the tlsdesc asm the offset to access the dtv changed too.
* work around arm gcc's rejection of r7 asm constraints in thumb modeRich Felker2018-05-011-14/+39
| | | | | | | | | | | | | | | | | | | | | | | in thumb mode, r7 is the ABI frame pointer register, and unless frame pointer is disabled, gcc insists on treating it as a fixed register, refusing to spill it to satisfy constraints. unfortunately, r7 is also used in the syscall ABI for passing the syscall number. up til now we just treated this as a requirement to disable frame pointer when generating code as thumb, but it turns out gcc forcibly enables frame pointer, and the fixed register constraint that goes with it, for functions which contain VLAs. this produces an unacceptable arch-specific constraint that (non-arm-specific) source files making syscalls cannot use VLAs. as a workaround, avoid r7 register constraints when producing thumb code and instead save/restore r7 in a temp register as part of the asm block. at some point we may want/need to support armv6-m/thumb1, so the asm has been tweaked to be thumb1-compatible while also near-optimal for thumb2: it allows the temp and/or syscall number to be in high registers (necessary since r0-r5 may all be used for syscalll args) and in thumb2 mode allows the syscall number to be an 8-bit immediate.
* arm: use a_ll/a_sc atomics when building for ARMv6T2Andre McCurdy2018-04-191-1/+1
| | | | | ARMv6 cores with support for Thumb2 can take advantage of the "ldrex" and "strex" based implementations of a_ll and a_sc.
* arm: respect both __ARM_ARCH_6KZ__ and __ARM_ARCH_6ZK__ macrosAndre McCurdy2018-04-192-2/+2
| | | | | | | | | | | | __ARM_ARCH_6ZK__ is a gcc specific historical typo which may not be defined by other compilers. https://gcc.gnu.org/ml/gcc-patches/2015-07/msg02237.html To avoid unexpected results when building for ARMv6KZ with clang, the correct form of the macro (ie 6KZ) needs to be tested. The incorrect form of the macro (ie 6ZK) still needs to be tested for compatibility with pre-2015 versions of gcc.
* provide optimized a_ctz_32 for armAndre McCurdy2018-04-191-0/+12
| | | | | | Provide an ARM specific a_ctz_32 helper function for architecture versions for which it can be implemented efficiently via the "rbit" instruction (ie all Thumb-2 capable versions of ARM v6 and above).
* remove a_ctz_l from arch specific atomic_arch.hAndre McCurdy2018-04-192-5/+5
| | | | | | | | Update atomic.h to provide a_ctz_l in all cases (atomic_arch.h should now only provide a_ctz_32 and/or a_ctz_64). The generic version of a_ctz_32 now takes advantage of a_clz_32 if available and the generic a_ctz_64 now makes use of a_ctz_32.
* fix minor namespace issues in termios.hRich Felker2018-03-106-0/+12
| | | | | | | | | | the output delay features (NL*, CR*, TAB*, BS*, and VT*) are XSI-shaded. VT* is in the V* namespace reservation but the rest need to be suppressed in base POSIX namespace. unfortunately this change introduces feature test macro checks into another bits header. at some point these checks should be simplified by having features.h handle the "FTM X implies Y" relationships.
* use PAGESIZE rather than PAGE_SIZE in user.h bitsRich Felker2018-03-104-8/+8
| | | | align with commit c9c2cd3e6955cb1d57b8be01d4b072bf44058762.
* reverse definition dependency between PAGESIZE and PAGE_SIZERich Felker2018-03-106-6/+6
| | | | | | PAGESIZE is actually the version defined in POSIX base, with PAGE_SIZE being in the XSI option. use PAGESIZE as the underlying definition to facilitate making exposure of PAGE_SIZE conditional.
* aarch64: add sve_context struct and related defines from linux v4.15Szabolcs Nagy2018-02-221-0/+39
| | | | | signal context definitions for scalable vector extension new in commit d0b8cd3187889476144bd9b13bf36a932c3e7952
* aarch64: update hwcap.h for linux v4.15Szabolcs Nagy2018-02-221-0/+6
| | | | | | HWCAP_SVE is new in linux commit 43994d824e8443263dc98b151e6326bf677be52e HWCAP_SHA3, HWCAP_SM3, HWCAP_SM4, HWCAP_ASIMDDP and HWCAP_SHA512 are new in f5e035f8694c3bdddc66ea46ecda965ee6853718
* arm: add get_tls syscall from linux v4.15Szabolcs Nagy2018-02-221-0/+1
| | | | | for systems without tp register or kuser helper, new in linux commit 8fcd6c45f5a65621ec809b7866a3623e9a01d4ed
* powerpc: update hwcap.h for linux v4.15Szabolcs Nagy2018-02-222-0/+6
| | | | | | | PPC_FEATURE2_HTM_NO_SUSPEND is new in linux commit cba6ac4869e45cc93ac5497024d1d49576e82666 PPC_FEATURE2_DARN and PPC_FEATURE2_SCV were new in v4.12 in commit a4700a26107241cc7b9ac8528b2c6714ff99983d
* s390x: add s390_sthyi system call from v4.15Szabolcs Nagy2018-02-221-0/+1
| | | | | to store hypervisor information, added in linux commit 3d8757b87d7fc15a87928bc970f060bc9c6dc618
* add MAP_SYNC and MAP_SHARED_VALIDATE from linux v4.15Szabolcs Nagy2018-02-225-0/+5
| | | | | | | | for synchronous page faults, new in linux commit 1c9725974074a047f6080eecc62c50a8e840d050 and b6fb293f2497a9841d94f6b57bd2bb2cd222da43 note that only targets that use asm-generic/mman.h have this new flag defined, so undef it on other targets (mips*, powerpc*).
* mips,powerpc: fix TIOCSER_TEMT in termios.hSzabolcs Nagy2018-02-225-5/+5
| | | | | | use the same token to define TIOCSER_TEMT as is used in ioctl.h so when both headers are included there are no redefinition warnings during musl build.
* aarch64: add HWCAP_DCPOP from linux v4.14Szabolcs Nagy2018-02-221-0/+1
| | | | | indicates ARMv8.2-DCPoP persistent memory support extension. new in linux commit 7aac405ebb3224037efd56b73d82d181111cdac3
* aarch64: fix mismatched type of ucontext_t uc_link memberWilliam Pitcock2018-01-311-1/+1
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* fix x32 unistd macros to report as ILP32 not LP64Nicholas Wilson2017-12-141-2/+2
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