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* fix conflicting mips and powerpc definitions for TIOCSER_TEMT macroSamuel Holland2019-07-105-5/+5
| | | | | | | | Commit 3517d74a5e04a377192d1f4882ad6c8dc22ce69a changed the token in sys/ioctl.h from 0x01 to 1, so bits/termios.h no longer matches. Revert the bits/termios.h change to keep the headers in sync. This reverts commit 9eda4dc69c33852c97c6f69176bf45ffc80b522f.
* remove spurious MAP_32BIT definition from riscv64 archRich Felker2019-07-041-1/+0
| | | | | | this was apparently copied from x86_64; it's not part of the kernel API for riscv64. this change eliminates the need for a riscv64-specific bits header and lets it use the generic one.
* add new syscall numbers from linux v5.1Szabolcs Nagy2019-07-0115-0/+327
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | syscall numbers are now synced up across targets (starting from 403 the numbers are the same on all targets other than an arch specific offset) IPC syscalls sem*, shm*, msg* got added where they were missing (except for semop: only semtimedop got added), the new semctl, shmctl, msgctl imply IPC_64, see linux commit 0d6040d4681735dfc47565de288525de405a5c99 arch: add split IPC system calls where needed new 64bit time_t syscall variants got added on 32bit targets, see linux commit 48166e6ea47d23984f0b481ca199250e1ce0730a y2038: add 64-bit time_t syscalls to all 32-bit architectures new async io syscalls got added, see linux commit 2b188cc1bb857a9d4701ae59aa7768b5124e262e Add io_uring IO interface linux commit edafccee56ff31678a091ddb7219aba9b28bc3cb io_uring: add support for pre-mapped user IO buffers a new syscall got added that uses the fd of /proc/<pid> as a stable handle for processes: allows sending signals without pid reuse issues, intended to eventually replace rt_sigqueueinfo, kill, tgkill and rt_tgsigqueueinfo, see linux commit 3eb39f47934f9d5a3027fe00d906a45fe3a15fad signal: add pidfd_send_signal() syscall on some targets (arm, m68k, s390x, sh) some previously missing syscall numbers got added as well.
* mips64: fix syscall numbers of io_pgetevents and rseqSzabolcs Nagy2019-07-011-2/+2
| | | | | | | | | the numbers added in commit d149e69c02eb558114f20ea718810e95538a3b2f add io_pgetevents and rseq syscall numbers from linux v4.18 were incorrect.
* s390x: drop SO_ definitions from bits/socket.hSzabolcs Nagy2019-07-011-28/+0
| | | | the s390x definitions matched the generic ones in sys/socket.h.
* add riscv64 architecture supportRich Felker2019-06-1425-0/+835
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Author: Alex Suykov <alex.suykov@gmail.com> Author: Aric Belsito <lluixhi@gmail.com> Author: Drew DeVault <sir@cmpwn.com> Author: Michael Clark <mjc@sifive.com> Author: Michael Forney <mforney@mforney.org> Author: Stefan O'Rear <sorear2@gmail.com> This port has involved the work of many people over several years. I have tried to ensure that everyone with substantial contributions has been credited above; if any omissions are found they will be noted later in an update to the authors/contributors list in the COPYRIGHT file. The version committed here comes from the riscv/riscv-musl repo's commit 3fe7e2c75df78eef42dcdc352a55757729f451e2, with minor changes by me for issues found during final review: - a_ll/a_sc atomics are removed (according to the ISA spec, lr/sc are not safe to use in separate inline asm fragments) - a_cas[_p] is fixed to be a memory barrier - the call from the _start assembly into the C part of crt1/ldso is changed to allow for the possibility that the linker does not place them nearby each other. - DTP_OFFSET is defined correctly so that local-dynamic TLS works - reloc.h LDSO_ARCH logic is simplified and made explicit. - unused, non-functional crti/n asm files are removed. - an empty .sdata section is added to crt1 so that the __global_pointer reference is resolvable. - indentation style errors in some asm files are fixed.
* make powerpc64 vrregset_t logical layout match expected APIRich Felker2019-05-221-1/+4
| | | | | | | | | between v2 and v3 of the powerpc64 port patch, the change was made from a 32x4 array of 32-bit unsigned ints for vrregs[] to a 32-element array of __int128. this mismatches the API applications working with mcontext_t expect from glibc, and seems to have been motivated by a misinterpretation of a comment on how aarch64 did things as a suggestion to do the same on powerpc64.
* fix vrregset_t layout and member naming on powerpc64Rich Felker2019-05-221-4/+8
| | | | | | | | | | | | | | | | | | the mistaken layout seems to have been adapted from 32-bit powerpc, where vscr and vrsave are packed into the same 128-bit slot in a way that looks like it relies on non-overlapping-ness of the value bits in big endian. the powerpc64 port accounted for the fact that the 64-bit ABI puts each in its own 128-bit slot, but ordered them incorrectly (matching the bit order used on the 32-bit ABI), and failed to account for vscr being padded according to endianness so that it can be accessed via vector moves. in addition to ABI layout, our definition used different logical member layout/naming from glibc, where vscr is a structure to facilitate access as a 32-bit word or a 128-bit vector. the inconsistency here was unintentional, so fix it.
* improve i386 inline syscall asm on non-broken compilersRich Felker2019-05-111-1/+20
| | | | | | | | | | | | | | | | | we have to avoid using ebx unconditionally in asm constraints for i386, because gcc 3 and 4 and possibly other simplistic compilers (pcc?) implement PIC via making ebx a fixed-use register, and disallow its use for anything else. rather than hard-coding knowledge of which compilers work (at least gcc 5+ and clang), perform a configure test; this should give us the good codegen on any new compilers we don't yet know about. swapping ebx and edx is kept for 1- and 2-arg syscalls because it avoids having any spills/stack-frame at all in small functions. for 6-arg, if ebx is directly usable, the complex shuffling introduced in commit c8798ef974d21c338a7d8d874a402978ffc6168e can be avoided, and ebp can be loaded the same way ebx is in 5-arg syscalls for compilers that don't support direct use of ebx.
* fix regression in i386 inline syscall asm producing invalid codeRich Felker2019-05-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 22e5bbd0deadcbd767864bd714e890b70e1fe1df inlined the i386 syscall mechanism, but wrongly assumed memory operands to the 5- and 6-argument syscall asm would be esp-based. however, nothing in the constraints prevented them from being ebx- or ebp-based, and in those cases, ebx and ebp could be clobbered before use of the memory operand was complete. in the 6-argument case, this prevented restoration of the original register values before the end of the asm block, breaking the asm contract since ebx and ebp are not marked as clobbered. (they can't be, because lots of compilers don't accept these registers in constraints or clobbers if PIC or frame pointer is enabled). doing this right is complicated by the fact that, after a single push, no operands which might be memory operands are usable. if they are esp-based, the value of esp has changed, rendering them invalid. introduce some new dances to load the registers. for the 5-arg case, push the operand that may be a memory operand first, and after that, it doesn't matter if the operand is invalid, since we'll just use the newly pushed value. for the 6-arg case, we need to put both operands in memory to begin with, like the old non-inline code prior to commit 22e5bbd0deadcbd767864bd714e890b70e1fe1df accepted, so that there's only one potentially memory-based operand to the asm. this can then be saved with a single push, and after that the values can be read off into the registers they're needed in. there's some size overhead, but still a lot less execution overhead than the old out-of-line code. doing it better depends on a modern compiler that lets you use ebx and ebp in asm constraints without restriction. the failure modes on compilers where this doesn't work are inconsistent and dangerous (on at least some gcc versions 4.x and earlier, wrong codegen!), so this is a delicate matter. it can be addressed later if needed.
* fix broken posix_fadvise on mips due to missing 7-arg syscall supportRich Felker2019-05-051-0/+25
| | | | | | | | commit 788d5e24ca19c6291cebd8d1ad5b5ed6abf42665 exposed the breakage at build time by removing support for 7-argument syscalls; however, the external __syscall function provided for mips before did not pass a 7th argument from the stack, so the behavior was just silently broken.
* fix build regression on mips n32 due to typo in new inline syscallRich Felker2019-05-051-1/+1
| | | | | commit 1bcdaeee6e659f1d856717c9aa562a068f2f3bd4 introduced the regression.
* fix passing of 64-bit syscall arguments on microblazeRich Felker2019-05-051-1/+1
| | | | | | | | | | | | | | | this has been wrong since the beginning of the microblaze port: the syscall ABI for microblaze does not align 64-bit arguments on even register boundaries. commit 788d5e24ca19c6291cebd8d1ad5b5ed6abf42665 exposed the problem by introducing references to a nonexistent __syscall7. the ABI is not documented well anywhere, but I was able to confirm against both strace source and glibc source that microblaze is not using the alignment. per the syscall(2) man page, posix_fadvise, ftruncate, pread, pwrite, readahead, sync_file_range, and truncate were all affected and either did not work at all, or only worked by chance, e.g. when the affected argument slots were all zero.
* fix regression in s390x SO_PEERSEC definitionRich Felker2019-04-231-0/+1
| | | | | | | analogous to commit efda534b212f713fe2b92a62b06e45f656b763ce for powerpc. commit 587f5a53bc3a68d80b239ba515d583df690a96df moved the definition of SO_PEERSEC to bits/socket.h for archs where the SO_* macros differ.
* math: add fp_arch.h with fp_barrier and fp_force_evalSzabolcs Nagy2019-04-172-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C99 has ways to support fenv access, but compilers don't implement it and assume nearest rounding mode and no fp status flag access. (gcc has -frounding-math and then it does not assume nearest rounding mode, but it still assumes the compiled code itself does not change the mode. Even if the C99 mechanism was implemented it is not ideal: it requires all code in the library to be compiled with FENV_ACCESS "on" to make it usable in non-nearest rounding mode, but that limits optimizations more than necessary.) The math functions should give reasonable results in all rounding modes (but the quality may be degraded in non-nearest rounding modes) and the fp status flag settings should follow the spec, so fenv side-effects are important and code transformations that break them should be prevented. Unfortunately compilers don't give any help with this, the best we can do is to add fp barriers to the code using volatile local variables (they create a stack frame and undesirable memory accesses to it) or inline asm (gcc specific, requires target specific fp reg constraints, often creates unnecessary reg moves and multiple barriers are needed to express that an operation has side-effects) or extern call (only useful in tail-call position to avoid stack-frame creation and does not work with lto). We assume that in a math function if an operation depends on the input and the output depends on it, then the operation will be evaluated at runtime when the function is called, producing all the expected fenv side-effects (this is not true in case of lto and in case the operation is evaluated with excess precision that is not rounded away). So fp barriers are needed (1) to prevent the move of an operation within a function (in case it may be moved from an unevaluated code path into an evaluated one or if it may be moved across a fenv access), (2) force the evaluation of an operation for its side-effect when it has no input dependency (may be constant folded) or (3) when its output is unused. I belive that fp_barrier and fp_force_eval can take care of these and they should not be needed in hot code paths.
* implement inline 5- and 6-argument syscalls for mipsn32 and mips64Rich Felker2019-04-102-29/+68
| | | | | | | | | | n32 and n64 ABIs add new argument registers vs o32, so that passing on the stack is not necessary, so it's not clear why the 5- and 6-argument versions were special-cased to begin with; it seems to have been pattern-copying from arch/mips (o32). i've treated the new argument registers like the first 4 in terms of clobber status (non-clobbered). hopefully this is correct.
* cleanup mips64 syscall_arch functionsRich Felker2019-04-101-18/+9
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* implement inline 5- and 6-argument syscalls for mipsRich Felker2019-04-101-6/+33
| | | | | | | | the OABI passes these on the stack, using the convention that their position on the stack is as if the first four arguments (in registers) also had stack slots. originally this was deemed too awkward to do inline, falling back to external __syscall, but it's not that bad and now that external __syscall is being removed, it's necessary.
* use inline syscalls for powerpc (32-bit)Rich Felker2019-04-101-2/+84
| | | | | | the inline syscall code is copied directly from powerpc64. the extent of register clobber specifiers may be excessive on both; if that turns out to be the case it can be fixed later.
* remove cruft for supposedly-buggy clang from or1k & microblaze syscall_archRich Felker2019-04-102-18/+0
| | | | | | | | | it was never demonstrated to me that this workaround was needed, and seems likely that, if there ever was any clang version for which it was needed, it's old enough to be unusably buggy in other ways. if it turns out some compilers actually can't do the register allocation right, we'll need to replace this with inline shuffling code, since the external __syscall dependency is being removed.
* overhaul i386 syscall mechanism not to depend on external asm sourceRich Felker2019-04-101-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this is the first part of a series of patches intended to make __syscall fully self-contained in the object file produced using syscall.h, which will make it possible for crt1 code to perform syscalls. the (confusingly named) i386 __vsyscall mechanism, which this commit removes, was introduced before the presence of a valid thread pointer was mandatory; back then the thread pointer was setup lazily only if threads were used. the intent was to be able to perform syscalls using the kernel's fast entry point in the VDSO, which can use the sysenter (Intel) or syscall (AMD) instruction instead of int $128, but without inlining an access to the __syscall global at the point of each syscall, which would incur a significant size cost from PIC setup everywhere. the mechanism also shuffled registers/calling convention around to avoid spills of call-saved registers, and to avoid allocating ebx or ebp via asm constraints, since there are plenty of broken-but-supported compiler versions which are incapable of allocating ebx with -fPIC or ebp with -fno-omit-frame-pointer. the new mechanism preserves the properties of avoiding spills and avoiding allocation of ebx/ebp in constraints, but does it inline, using some fairly simple register shuffling, and uses a field of the thread structure rather than global data for the vdso-provided syscall code address. for now, the external __syscall function is refactored not to use the old __vsyscall so it can be kept, but the intent is to remove it too.
* aarch64: add HWCAP_ definitions from linux v5.0Szabolcs Nagy2019-03-131-0/+3
| | | | | | | | HWCAP_SB - speculation barrier instruction available added in linux commit bd4fb6d270bc423a9a4098108784f7f9254c4e6d HWCAP_PACA, HWCAP_PACG - pointer authentication instructions available (address and generic) added in linux commit 7503197562567b57ec14feb3a9d5400ebc56812f
* aarch64, or1k: add kexec_file_load syscall number from linux v5.0Szabolcs Nagy2019-03-132-0/+2
| | | | added in linux commit 4e21565b7fd4d9045765f697887e74a704135fe2
* powerpc: add PTRACE_SYSEMU from linux v4.20Szabolcs Nagy2019-03-132-0/+4
| | | | added in linux commit 5521eb4bca2db733952f068c37bdf3cd656ad23c
* aarch64: add HWCAP_SSBS from linux v4.20Szabolcs Nagy2019-03-131-0/+1
| | | | | for armv8.5 speculative store bypass PSTATE bit support, added in linux commit d71be2b6c0e19180b5f80a6d42039cc074a693a2
* bits/ioctl.h: add TIOC{G,S}ISO7816 from linux v4.20Szabolcs Nagy2019-03-131-0/+2
| | | | | | | | | | | | | | | | | | | | | ISO7816 smart cards ioctls. linux commit ad8c0eaa0a418ae8ef3f9217638bb86439399eac the actual kernel definitions are #define TIOCGISO7816 _IOR('T', 0x42, struct serial_iso7816) #define TIOCSISO7816 _IOWR('T', 0x43, struct serial_iso7816) where struct serial_iso7816 is defined in linux/serial.h as struct serial_iso7816 { __u32 flags; __u32 tg; __u32 sc_fi; __u32 sc_di; __u32 clk; __u32 reserved[5]; };
* arm: add io_pgetevents syscall number from v4.19Szabolcs Nagy2019-03-131-0/+1
| | | | wired up in linux commit 73aeb2cbcdc9be391b3d32a55319a59ce425426f
* aarch64, or1k: define rseq syscall number following linux v4.19Szabolcs Nagy2019-03-132-0/+2
| | | | added in linux commit db7a2d1809a5b6b08d138ff68837f805fc073351
* fix POSIX_FADV_DONTNEED/_NOREUSE on s390xJonathan Neuschäfer2019-03-131-0/+3
| | | | | | | | | On s390x, POSIX_FADV_DONTNEED and POSIX_FADV_NOREUSE have different values than on all other architectures that Linux supports. Handle this difference by wrapping their definitions in include/fcntl.h in #ifdef, so that arch/s390x/bits/fcntl.h can override them.
* move arch-invariant definitions out of bits/ioctl.hBobby Bingham2019-02-077-682/+0
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* add io_pgetevents and rseq syscall numbers from linux v4.18Szabolcs Nagy2018-12-0913-0/+23
| | | | | | | | io_pgetevents is new in linux commit 7a074e96dee62586c935c80cecd931431bfdd0be rseq is new in linux commit d7822b1e24f2df5df98c76f0e94a5416349ff759
* make thread-pointer-loading asm non-volatileRich Felker2018-10-1614-19/+19
| | | | | | | | | | this will allow the compiler to cache and reuse the result, meaning we no longer have to take care not to load it more than once for the sake of archs where the load may be expensive. depends on commit 1c84c99913bf1cd47b866ed31e665848a0da84a2 for correctness, since otherwise the compiler could hoist loads during stage 3 of dynamic linking before the initial thread-pointer setup.
* remove ancient clang workaround from powerpc pthread_arch.h asmRich Felker2018-10-161-5/+0
| | | | | versions of clang all the way back to 3.1 lack the bug this was purportedly working around.
* add TLSDESC support for 32-bit armRich Felker2018-10-011-1/+3
| | | | | | | | | | | | | | | unlike other asm where the baseline ISA is used, these functions are hot paths and use ISA-level specializations. call-clobbered vfp registers are saved before calling __tls_get_new, since there is no guarantee it won't use them. while setjmp/longjmp have to use hwcap to decide whether to the fpu is in use, since application code could be using vfp registers even if libc was compiled as pure softfloat, __tls_get_new is part of libc and can be assumed not to have access to vfp registers if tlsdesc.S does not. thus it suffices just to check the predefined preprocessor macros. the check for __ARM_PCS_VFP is redundant; !__SOFTFP__ must always be true if the target ISA level includes fpu instructions/registers.
* add arm and sh bits/ptrace.hSzabolcs Nagy2018-09-202-0/+30
| | | | | | These should have been added in commit df6d9450ea19fd71e52cf5cdb4c85beb73066394 that added target specific PTRACE_ macros, but somehow got missed.
* fix broken atomic store on powerpc[64]Rich Felker2018-09-142-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | in our memory model, all atomics are supposed to be full barriers; stores are not release-only. this is important because store is used as an unlock operation in places where it needs to acquire the waiter count to determine if a futex wake is needed. at least in the malloc-internal locks, but possibly elsewhere, soft deadlocks from missing futex wake (breakable by poking the threads to restart the syscall, e.g. by attaching a tracer) were reported to occur. once the malloc lock is replaced with Jens Gustedt's new lock implementation (see commit 47d0bcd4762f223364e5b58d5a381aaa0cbd7c38), malloc will not be affected by the issue, but it's not clear that other uses won't be. reducing the strength of the ordering properties required from a_store would require a thorough analysis of how it's used. to fix the problem, I'm removing the powerpc[64]-specific a_store definition; now, the top-level atomic.h will implement a_store using a_barrier on both sides of the store. it's not clear to me yet whether there might be issues with the other atomics. it's possible that a_post_llsc needs to be replaced with a full barrier to guarantee the formal semanics we want, but either way I think the difference is unlikely to impact the way we use them.
* apply hidden visibility to sigreturn code fragmentsRich Felker2018-09-126-6/+18
| | | | | | | these were overlooked in the declarations overhaul work because they are not properly declared, and the current framework even allows their declared types to vary by arch. at some point this should be cleaned up, but I'm not sure what the right way would be.
* define and use internal macros for hidden visibility, weak refsRich Felker2018-09-055-8/+9
| | | | | | | | | this cleans up what had become widespread direct inline use of "GNU C" style attributes directly in the source, and lowers the barrier to increased use of hidden visibility, which will be useful to recovering some of the efficiency lost when the protected visibility hack was dropped in commit dc2f368e565c37728b0d620380b849c3a1ddd78f, especially on archs where the PLT ABI is costly.
* fix async thread cancellation on sh-fdpicRich Felker2018-08-291-0/+5
| | | | | | | | | | | | | | if __cp_cancel was reached via __syscall_cp, r12 will necessarily still contain a GOT pointer (for libc.so or for the static-linked main program) valid for entering __cancel. however, in the case of async cancellation, r12 may contain any scratch value; it's not necessarily even a valid GOT pointer for the code that was interrupted. unlike in commit 0ec49dab6794166d67fae4764ce7fdea42ea6103 where the corresponding issue was fixed for powerpc64, there is fundamentally no way for fdpic code to recompute its GOT pointer. so a new mechanism is introduced for cancel_handler to write a GOT register value into the interrupted context on archs where it is needed.
* move inclusion of linux headers for kd.h, soundcard.h, vt.h to bitsmidipix2018-07-203-0/+3
| | | | | | | | | | | | maintainer's note: while musl does not use the linux kernel headers, it does provide these three sys/* headers which do nothing but include the corresponding linux/* headers, since the sys/* versions are the ones documented for application use (and they arguably provide interfaces that are not linux-specific but common to other unices). these headers should probably not be provided by libc (rather by a separate package), but as long as they are, use the bits header framework as an aid to out-of-tree ports of musl for non-linux systems that want to implement them in some other way.
* add support for arch-specific ptrace command macrosSzabolcs Nagy2018-07-1711-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | sys/ptrace.h is target specific, use bits/ptrace.h to add target specific macro definitions. these macros are kept in the generic sys/ptrace.h even though some targets don't support them: PTRACE_GETREGS PTRACE_SETREGS PTRACE_GETFPREGS PTRACE_SETFPREGS PTRACE_GETFPXREGS PTRACE_SETFPXREGS so no macro definition got removed in this patch on any target. only s390x has a numerically conflicting macro definition (PTRACE_SINGLEBLOCK). the PT_ aliases follow glibc headers, otherwise the definitions come from linux uapi headers except ones that are skipped in glibc and there is no real kernel support (s390x PTRACE_*_AREA) or need special type definitions (mips PTRACE_*_WATCH_*) or only relevant for linux 2.4 compatibility (PTRACE_OLDSETOPTIONS).
* fix regression in powerpc[64] SO_PEERSEC definitionRich Felker2018-06-262-0/+2
| | | | | | | commit 587f5a53bc3a68d80b239ba515d583df690a96df moved the definition of SO_PEERSEC to bits/socket.h for archs where the SO_* macros differ from their standard values, but failed to add copies of the generic definition for powerpc and powerpc64.
* fix value of SO_PEERSEC on mips archsRich Felker2018-06-263-0/+3
| | | | adapted from patch by Matthias Schiffer.
* add m68k reg.h and user.hRich Felker2018-06-262-0/+78
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* fix m68k float.h long double exponent rangeRich Felker2018-06-201-2/+2
| | | | | unlike the x86 variant, the m68k ld80 format allows (biased) exponent zero with mantissa msb set, thereby extending the normal range.
* work around broken kernel struct ipc_perm on some big endian archsRich Felker2018-06-204-0/+7
| | | | | | | | | | | | | | | the mode member of struct ipc_perm is specified by POSIX to have type mode_t, which is uniformly defined as unsigned int. however, Linux defines it with type __kernel_mode_t, and defines __kernel_mode_t as unsigned short on some archs. since there is a subsequent padding field, treating it as a 32-bit unsigned int works on little endian archs, but the order is backwards on big endian archs with the erroneous definition. since multiple archs are affected, remedy the situation with fixup code in the affected functions (shmctl, semctl, and msgctl) rather than repeating the same shims in syscall_arch.h for every affected arch.
* s390x: add kexec_file_load syscall number from linux v4.17Szabolcs Nagy2018-06-191-0/+1
| | | | new in linux commit 71406883fd35794d573b3085433c41d0a3bf6c21
* mips: add HWCAP_ flags from linux v4.17Szabolcs Nagy2018-06-193-0/+3
| | | | new in linux commit 256211f2b0b251e532d1899b115e374feb16fa7a
* aarch64: add HWCAP_ flags from linux v4.17Szabolcs Nagy2018-06-191-0/+4
| | | | | hwcaps for armv8.4, new in linux commit 7206dc93a58fb76421c4411eefa3c003337bcb2d
* powerpc: add pkey syscall numbers from linux v4.16Szabolcs Nagy2018-06-192-0/+6
| | | | | | add pkey_mprotect, pkey_alloc, pkey_free syscall numbers, new in linux commits 3350eb2ea127978319ced883523d828046af4045 and 9499ec1b5e82321829e1c1510bcc37edc20b6f38
generated by cgit-pink 1.4.1 (git 2.36.1) at 2024-11-05 13:01:31 +0000