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* add explicit barrier operation to internal atomic.h APIRich Felker2014-10-101-1/+3
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* add working a_spin() atomic for non-x86 targetsRich Felker2014-08-251-0/+1
| | | | | | | | | | | | | conceptually, a_spin needs to be at least a compiler barrier, so the compiler will not optimize out loops (and the load on each iteration) while spinning. it should also be a memory barrier, or the spinning thread might keep spinning without noticing stores from other threads, thus delaying for longer than it should. ideally, an optimal a_spin implementation that avoids unnecessary cache/memory contention should be chosen for each arch, but for now, the easiest thing is to perform a useless a_cas on the calling thread's stack.
* clean up unused and inconsistent atomics in arch dirsRich Felker2014-07-271-6/+0
| | | | | | | | | | | the a_cas_l, a_swap_l, a_swap_p, and a_store_l operations were probably used a long time ago when only i386 and x86_64 were supported. as other archs were added, support for them was inconsistent, and they are obviously not in use at present. having them around potentially confuses readers working on new ports, and the type-punning hacks and inconsistent use of types in their definitions is not a style I wish to perpetuate in the source tree, so removing them seems appropriate.
* fix missing barrier instructions in mips atomic asmRich Felker2014-07-191-14/+18
| | | | | | | | previously I had wrongly assumed the ll/sc instructions also provided memory synchronization; apparently they do not. this commit adds sync instructions before and after each atomic operation and changes the atomic store to simply use sync before and after a plain store, rather than a useless compare-and-swap.
* use memory constraints for mips atomic asmRich Felker2014-07-191-24/+24
| | | | | | | | | | | | | | | | despite lacking the semantic content that the asm accesses the pointed-to object rather than just using its address as a value, the mips asm was not actually broken. the asm blocks were declared volatile, meaning that the compiler must treat them as having unknown side effects. however changing the asm to use memory constraints is desirable not just from a semantic correctness and consistency standpoint, but also produces better code. the compiler is able to use base/offset addressing expressions for the atomic object's address rather than having to load the address into a single register. this improves access to global locks in static libc, and access to non-zero-offset atomic fields in synchronization primitives, etc.
* add missing a_or_l to atomic.h for non-x86 archsRich Felker2013-08-111-0/+5
| | | | this is needed for recently committed sigaction code
* avoid need for -march=mips2 to compile mips atomic.h asmRich Felker2012-08-111-0/+8
| | | | | | linux guarantees ll/sc are always available. on mips1, they will be emulated by the kernel. thus they are part of the linux mips1 abi and safe to use.
* fix broken mips a_fetch_addRich Felker2012-07-121-7/+7
| | | | sc was overwriting the result
* initial version of mips (o32) port, based on work by Richard Pennington (rdp)Rich Felker2012-07-111-0/+191
basically, this version of the code was obtained by starting with rdp's work from his ellcc source tree, adapting it to musl's build system and coding style, auditing the bits headers for discrepencies with kernel definitions or glibc/LSB ABI or large file issues, fixing up incompatibility with the old binutils from aboriginal linux, and adding some new special cases to deal with the oddities of sigaction and pipe syscall interfaces on mips. at present, minimal test programs work, but some interfaces are broken or missing. threaded programs probably will not link.