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authorStefan Kristiansson <stefan.kristiansson@saunalahti.fi>2014-07-17 22:09:10 +0300
committerRich Felker <dalias@aerifal.cx>2014-07-18 14:10:23 -0400
commit200d15479c0bc48471ee7b8e538ce33af990f82e (patch)
tree864cc38895b9277384ed3a956f4ad324de2c4455 /src/thread/or1k/clone.s
parent7bece9c2095ee81f14b1088f6b0ba2f37fecb283 (diff)
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add or1k (OpenRISC 1000) architecture port
With the exception of a fenv implementation, the port is fully featured.
The port has been tested in or1ksim, the golden reference functional
simulator for OpenRISC 1000.
It passes all libc-test tests (except the math tests that
requires a fenv implementation).

The port assumes an or1k implementation that has support for
atomic instructions (l.lwa/l.swa).

Although it passes all the libc-test tests, the port is still
in an experimental state, and has yet experienced very little
'real-world' use.
Diffstat (limited to 'src/thread/or1k/clone.s')
-rw-r--r--src/thread/or1k/clone.s30
1 files changed, 30 insertions, 0 deletions
diff --git a/src/thread/or1k/clone.s b/src/thread/or1k/clone.s
new file mode 100644
index 00000000..02f380bd
--- /dev/null
+++ b/src/thread/or1k/clone.s
@@ -0,0 +1,30 @@
+/* int clone(fn, stack, flags, arg, ptid, tls, ctid)
+ *           r3  r4     r5     r6   sp+0  sp+4 sp+8
+ * sys_clone(flags, stack, ptid, ctid, tls)
+ */
+.global __clone
+.type   __clone,@function
+__clone:
+	l.addi	r4, r4, -8
+	l.sw	0(r4), r3
+	l.sw	4(r4), r6
+	/* (fn, st, fl, ar, pt, tl, ct) => (fl, st, pt, ct, tl) */
+	l.ori	r3, r5, 0
+	l.lwz	r5, 0(r1)
+	l.lwz	r6, 8(r1)
+	l.lwz	r7, 4(r1)
+	l.ori	r11, r0, 220 /* __NR_clone */
+	l.sys	1
+
+	l.sfeqi	r11, 0
+	l.bf	1f
+	 l.nop
+	l.jr	r9
+	 l.nop
+
+1:	l.lwz	r11, 0(r1)
+	l.jalr	r11
+	 l.lwz	r3, 4(r1)
+
+	l.ori	r11, r0, 93 /* __NR_exit */
+	l.sys	1