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author | Rich Felker <dalias@aerifal.cx> | 2012-08-05 02:37:14 -0400 |
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committer | Rich Felker <dalias@aerifal.cx> | 2012-08-05 02:37:14 -0400 |
commit | 5a3a37861573722ca417d774701b952f39abea7e (patch) | |
tree | bd1d6070c2a5b681d784262d748736caa3426f34 /src/setjmp/arm | |
parent | 8a996b7e6c3cf9f852bfcd2adf2ed68bf4725754 (diff) | |
download | musl-5a3a37861573722ca417d774701b952f39abea7e.tar.gz musl-5a3a37861573722ca417d774701b952f39abea7e.tar.xz musl-5a3a37861573722ca417d774701b952f39abea7e.zip |
floating point support for arm setjmp/longjmp
not heavily tested, but at least they don't seem to break anything on soft float targets with or without coprocessors. they check the auxv AT_HWCAP flags to determine which coprocessor, if any, is available.
Diffstat (limited to 'src/setjmp/arm')
-rw-r--r-- | src/setjmp/arm/longjmp.s | 28 | ||||
-rw-r--r-- | src/setjmp/arm/setjmp.s | 28 |
2 files changed, 54 insertions, 2 deletions
diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s index 690a0089..84ddc22f 100644 --- a/src/setjmp/arm/longjmp.s +++ b/src/setjmp/arm/longjmp.s @@ -8,6 +8,32 @@ longjmp: movs r0,r1 moveq r0,#1 ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} - tst lr,#1 + + adr r1,1f + ldr r2,1f + ldr r1,[r1,r2] + + tst r1,#0x260 + beq 3f + tst r1,#0x20 + beq 2f + ldc p2, cr4, [ip], #48 +2: tst r1,#0x40 + beq 2f + ldc p11, cr8, [ip], #64 + ldmia ip!, {r2,r3} + mcr p10, 7, r3, cr1, cr0, 0 +2: tst r1,#0x200 + beq 3f + ldcl p1, cr10, [ip], #8 + ldcl p1, cr11, [ip], #8 + ldcl p1, cr12, [ip], #8 + ldcl p1, cr13, [ip], #8 + ldcl p1, cr14, [ip], #8 + ldcl p1, cr15, [ip], #8 +3: tst lr,#1 moveq pc,lr bx lr + +.hidden __hwcap +1: .word __hwcap-1b diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s index 6985caab..904ff102 100644 --- a/src/setjmp/arm/setjmp.s +++ b/src/setjmp/arm/setjmp.s @@ -10,6 +10,32 @@ setjmp: mov ip,r0 stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} mov r0,#0 - tst lr,#1 + + adr r1,1f + ldr r2,1f + ldr r1,[r1,r2] + + tst r1,#0x260 + beq 3f + tst r1,#0x20 + beq 2f + stc p2, cr4, [ip], #48 +2: tst r1,#0x40 + beq 2f + stc p11, cr8, [ip], #64 + mrc p10, 7, r2, cr1, cr0, 0 + stmia ip!, {r0,r2} +2: tst r1,#0x200 + beq 3f + stcl p1, cr10, [ip], #8 + stcl p1, cr11, [ip], #8 + stcl p1, cr12, [ip], #8 + stcl p1, cr13, [ip], #8 + stcl p1, cr14, [ip], #8 + stcl p1, cr15, [ip], #8 +3: tst lr,#1 moveq pc,lr bx lr + +.hidden __hwcap +1: .word __hwcap-1b |