add support for mips and mips64 r6 isa

mips32r6 and mips64r6 are actually new isas at both the asm source and
opcode levels (pre-r6 code cannot run on r6) and thus need to be
treated as a new subarch. the following changes are made, some of
which yield code generation improvements for non-r6 targets too:

- add subarch logic in configure script and reloc.h files for dynamic
  linker name.

- suppress use of .set mips2 asm directives (used to allow mips2
  atomic instructions on baseline mips1 builds; the kernel has to
  emulate them on mips1) except when actually needed. they cause wrong
  instruction encodings on r6, and pessimize inlining on at least some
  compilers.

- only hard-code sync instruction encoding on mips1.

- use "ZC" constraint instead of "m" constraint for llsc memory
  operands on r6, where the ll/sc instructions no longer accept full
  16-bit offsets.

- only hard-code rdhwr instruction encoding with .word on targets
  (pre-r2) where it may need trap-and-emulate by the kernel.
  otherwise, just use the instruction mnemonic, and allow an arbitrary
  destination register to be used.

1 files changed, 2 insertions, 0 deletions

diff --git a/configure b/configure
index 213a8254..969671dd 100755
--- a/configure
+++ b/configure
@@ -612,11 +612,13 @@ trycppif __AARCH64EB__ "$t" && SUBARCH=${SUBARCH}_be
 fi
 
 if test "$ARCH" = "mips" ; then
+trycppif "__mips_isa_rev >= 6" "$t" && SUBARCH=${SUBARCH}r6
 trycppif "_MIPSEL || __MIPSEL || __MIPSEL__" "$t" && SUBARCH=${SUBARCH}el
 trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
 fi
 
 if test "$ARCH" = "mips64" ; then
+trycppif "__mips_isa_rev >= 6" "$t" && SUBARCH=${SUBARCH}r6
 trycppif "_MIPSEL || __MIPSEL || __MIPSEL__" "$t" && SUBARCH=${SUBARCH}el
 trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
 fi