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authorRich Felker <dalias@aerifal.cx>2021-09-23 19:11:46 -0400
committerRich Felker <dalias@aerifal.cx>2021-09-23 19:11:46 -0400
commit7be59733d71ada3a32a98622507399253f1d5e48 (patch)
tree8baa69b0f4bb7dacacee7f8a8650e8f951614d0b /arch/powerpc
parente3e7189c11d909199155327fd6a93dcc6b68c7b3 (diff)
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add SPE FPU support to powerpc-sf
When the soft-float ABI for PowerPC was added in commit
5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb, with Freescale cpus using
the alternative SPE FPU as the main use case, it was noted that we
could probably support hard float on them, but that it would involve
determining some difficult ABI constraints. This commit is the
completion of that work.

The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed
ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility
are problematic for the same reason they're problematic on ARM, where
optional float-related parts of the register file are "call-saved if
present". This requires testing __hwcap, which is now done.

In keeping with the existing powerpc-sf subarch definition, which did
not have fenv, the fenv macros are not defined for SPE and the SPEFSCR
control register is left (and assumed to start in) the default mode.
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/bits/fenv.h2
-rw-r--r--arch/powerpc/reloc.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/bits/fenv.h b/arch/powerpc/bits/fenv.h
index c5a3e5c5..5b15c69a 100644
--- a/arch/powerpc/bits/fenv.h
+++ b/arch/powerpc/bits/fenv.h
@@ -1,4 +1,4 @@
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 #define FE_ALL_EXCEPT 0
 #define FE_TONEAREST  0
 #else
diff --git a/arch/powerpc/reloc.h b/arch/powerpc/reloc.h
index 527b6b7c..fdfbf827 100644
--- a/arch/powerpc/reloc.h
+++ b/arch/powerpc/reloc.h
@@ -1,4 +1,4 @@
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 #define FP_SUFFIX "-sf"
 #else
 #define FP_SUFFIX ""