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authorRich Felker <dalias@aerifal.cx>2016-04-03 10:42:37 +0000
committerRich Felker <dalias@aerifal.cx>2016-04-03 10:42:37 +0000
commit6d99ad91e869aab35a4d76d34c3c9eaf29482bad (patch)
treef8e7665f23b5067b5ca39d2e7a19f7132fc9e2e3 /arch/mipsn32/atomic_arch.h
parentc718f9fc1b4bd913eff10d0c12763f90b2bc487c (diff)
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add support for mips and mips64 r6 isa
mips32r6 and mips64r6 are actually new isas at both the asm source and
opcode levels (pre-r6 code cannot run on r6) and thus need to be
treated as a new subarch. the following changes are made, some of
which yield code generation improvements for non-r6 targets too:

- add subarch logic in configure script and reloc.h files for dynamic
  linker name.

- suppress use of .set mips2 asm directives (used to allow mips2
  atomic instructions on baseline mips1 builds; the kernel has to
  emulate them on mips1) except when actually needed. they cause wrong
  instruction encodings on r6, and pessimize inlining on at least some
  compilers.

- only hard-code sync instruction encoding on mips1.

- use "ZC" constraint instead of "m" constraint for llsc memory
  operands on r6, where the ll/sc instructions no longer accept full
  16-bit offsets.

- only hard-code rdhwr instruction encoding with .word on targets
  (pre-r2) where it may need trap-and-emulate by the kernel.
  otherwise, just use the instruction mnemonic, and allow an arbitrary
  destination register to be used.
Diffstat (limited to 'arch/mipsn32/atomic_arch.h')
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