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author | Rich Felker <dalias@aerifal.cx> | 2016-01-21 23:30:30 +0000 |
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committer | Rich Felker <dalias@aerifal.cx> | 2016-01-21 23:30:30 +0000 |
commit | 397f0a6a7d798b0e3f636fe053cad9c483e011fb (patch) | |
tree | edb9ed99f49937f412f9e4532f89a0bc97485fb3 /arch/mips/atomic_arch.h | |
parent | aa0db4b5d08ff6ac180a93678d8fd1799569a530 (diff) | |
download | musl-397f0a6a7d798b0e3f636fe053cad9c483e011fb.tar.gz musl-397f0a6a7d798b0e3f636fe053cad9c483e011fb.tar.xz musl-397f0a6a7d798b0e3f636fe053cad9c483e011fb.zip |
overhaul arm atomics for new atomics framework
switch to ll/sc model so that new atomic.h can provide optimized versions of all the atomic primitives without needing an ll/sc loop written in asm for each one. all isa levels which use ldrex/strex now use the inline ll/sc model even if the type of barrier to use is not known until runtime (v6). the cas model is only used for arm v5 and earlier, and it has been optimized to make the call via inline asm with custom constraints rather than as a C function call.
Diffstat (limited to 'arch/mips/atomic_arch.h')
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