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author | Rich Felker <dalias@aerifal.cx> | 2013-08-28 03:34:57 -0400 |
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committer | Rich Felker <dalias@aerifal.cx> | 2013-08-28 03:34:57 -0400 |
commit | 90edf1cc15cec685c18ec2485ddce5b655963464 (patch) | |
tree | 97b728abcd94fbb0e41a2a1d14a7a15d70b24c36 /arch/arm | |
parent | 38e6acbf89afd3dfabb4f4d0506319c339b13663 (diff) | |
download | musl-90edf1cc15cec685c18ec2485ddce5b655963464.tar.gz musl-90edf1cc15cec685c18ec2485ddce5b655963464.tar.xz musl-90edf1cc15cec685c18ec2485ddce5b655963464.zip |
optimized C memcpy
unlike the old C memcpy, this version handles word-at-a-time reads and writes even for misaligned copies. it does not require that the cpu support misaligned accesses; instead, it performs bit shifts to realign the bytes for the destination. essentially, this is the C version of the ARM assembly language memcpy. the ideas are all the same, and it should perform well on any arch with a decent number of general-purpose registers that has a barrel shift operation. since the barrel shifter is an optional cpu feature on microblaze, it may be desirable to provide an alternate asm implementation on microblaze, but otherwise the C code provides a competitive implementation for "generic risc-y" cpu archs that should alleviate the urgent need for arch-specific memcpy asm.
Diffstat (limited to 'arch/arm')
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