1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
|
/* Raise given exceptions.
Copyright (C) 2000-2019 Free Software Foundation, Inc.
This file is part of the GNU C Library.
Contributed by Denis Joseph Barrow (djbarrow@de.ibm.com) and
Martin Schwidefsky (schwidefsky@de.ibm.com).
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, see
<http://www.gnu.org/licenses/>. */
#include <fenv_libc.h>
#include <float.h>
#include <math.h>
static __inline__ void
fexceptdiv (float d, float e)
{
__asm__ __volatile__ ("debr %0,%1" : : "f" (d), "f" (e) );
}
static __inline__ void
fexceptadd (float d, float e)
{
__asm__ __volatile__ ("aebr %0,%1" : : "f" (d), "f" (e) );
}
#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
static __inline__ void
fexceptround (double e)
{
float d;
/* Load rounded from double to float with M3 = round toward 0, M4 = Suppress
IEEE-inexact exception.
In case of e=0x1p128 and the overflow-mask bit is zero, only the
IEEE-overflow flag is set. If overflow-mask bit is one, DXC field is set to
0x20 "IEEE overflow, exact".
In case of e=0x1p-150 and the underflow-mask bit is zero, only the
IEEE-underflow flag is set. If underflow-mask bit is one, DXC field is set
to 0x10 "IEEE underflow, exact".
This instruction is available with a zarch machine >= z196. */
__asm__ __volatile__ ("ledbra %0,5,%1,4" : "=f" (d) : "f" (e) );
}
#endif
int
__feraiseexcept (int excepts)
{
/* Raise exceptions represented by EXPECTS. But we must raise only
one signal at a time. It is important that if the overflow/underflow
exception and the inexact exception are given at the same time,
the overflow/underflow exception follows the inexact exception. */
/* First: invalid exception. */
if (FE_INVALID & excepts)
fexceptdiv (0.0, 0.0);
/* Next: division by zero. */
if (FE_DIVBYZERO & excepts)
fexceptdiv (1.0, 0.0);
/* Next: overflow. */
if (FE_OVERFLOW & excepts)
{
#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
fexceptround (0x1p128);
#else
/* If overflow-mask bit is zero, both IEEE-overflow and IEEE-inexact flags
are set. If overflow-mask bit is one, DXC field is set to 0x2C "IEEE
overflow, inexact and incremented". */
fexceptadd (FLT_MAX, 1.0e32);
#endif
}
/* Next: underflow. */
if (FE_UNDERFLOW & excepts)
{
#ifdef HAVE_S390_MIN_Z196_ZARCH_ASM_SUPPORT
fexceptround (0x1p-150);
#else
/* If underflow-mask bit is zero, both IEEE-underflow and IEEE-inexact
flags are set. If underflow-mask bit is one, DXC field is set to 0x1C
"IEEE underflow, inexact and incremented". */
fexceptdiv (FLT_MIN, 3.0);
#endif
}
/* Last: inexact. */
if (FE_INEXACT & excepts)
fexceptdiv (2.0, 3.0);
/* Success. */
return 0;
}
libm_hidden_def (__feraiseexcept)
weak_alias (__feraiseexcept, feraiseexcept)
libm_hidden_weak (feraiseexcept)
|
