about summary refs log tree commit diff
path: root/sysdeps/powerpc/powerpc32/405/strcmp.S
blob: 629c7727f560f78fd36a019edb7df310609c4860 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
/* Optimized strcmp implementation for PowerPC476.
   Copyright (C) 2010-2023 Free Software Foundation, Inc.
   This file is part of the GNU C Library.

   The GNU C Library is free software; you can redistribute it and/or
   modify it under the terms of the GNU Lesser General Public
   License as published by the Free Software Foundation; either
   version 2.1 of the License, or (at your option) any later version.

   The GNU C Library is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   Lesser General Public License for more details.

   You should have received a copy of the GNU Lesser General Public
   License along with the GNU C Library.  If not, see
   <https://www.gnu.org/licenses/>.  */

#include <sysdep.h>

/* strcmp

       Register Use
       r0:temp return equality
       r3:source1 address, return equality
       r4:source2 address

       Implementation description
       Check 2 words from src1 and src2. If unequal jump to end and
       return src1 > src2 or src1 < src2.
       If null check bytes before null and then jump to end and
       return src1 > src2, src1 < src2 or src1 = src2.
       If src1 = src2 and no null, repeat. */

EALIGN (strcmp,5,0)
       neg     r7,r3
       clrlwi  r7,r7,20
       neg     r8,r4
       clrlwi  r8,r8,20
       srwi.   r7,r7,5
       beq     L(byte_loop)
       srwi.   r8,r8,5
       beq     L(byte_loop)
       cmplw   r7,r8
       mtctr   r7
       ble     L(big_loop)
       mtctr   r8

L(big_loop):
       lwz     r5,0(r3)
       lwz     r6,4(r3)
       lwz     r8,0(r4)
       lwz     r9,4(r4)
       dlmzb.  r12,r5,r6
       bne     L(end_check)
       cmplw   r5,r8
       bne     L(st1)
       cmplw   r6,r9
       bne     L(st1)
       lwz     r5,8(r3)
       lwz     r6,12(r3)
       lwz     r8,8(r4)
       lwz     r9,12(r4)
       dlmzb.  r12,r5,r6
       bne     L(end_check)
       cmplw   r5,r8
       bne     L(st1)
       cmplw   r6,r9
       bne     L(st1)
       lwz     r5,16(r3)
       lwz     r6,20(r3)
       lwz     r8,16(r4)
       lwz     r9,20(r4)
       dlmzb.  r12,r5,r6
       bne     L(end_check)
       cmplw   r5,r8
       bne     L(st1)
       cmplw   r6,r9
       bne     L(st1)
       lwz     r5,24(r3)
       lwz     r6,28(r3)
       addi    r3,r3,0x20
       lwz     r8,24(r4)
       lwz     r9,28(r4)
       addi    r4,r4,0x20
       dlmzb.  r12,r5,r6
       bne     L(end_check)
       cmplw   r5,r8
       bne     L(st1)
       cmplw   r6,r9
       bne     L(st1)
       bdnz    L(big_loop)
       b       L(byte_loop)

L(end_check):
       subfic  r12,r12,4
       blt     L(end_check2)
       rlwinm  r12,r12,3,0,31
       srw     r5,r5,r12
       srw     r8,r8,r12
       cmplw   r5,r8
       bne     L(st1)
       b       L(end_strcmp)

L(end_check2):
       addi    r12,r12,4
       cmplw   r5,r8
       rlwinm  r12,r12,3,0,31
       bne     L(st1)
       srw     r6,r6,r12
       srw     r9,r9,r12
       cmplw   r6,r9
       bne     L(st1)

L(end_strcmp):
       addi    r3,r0,0
       blr

L(st1):
       mfcr    r3
       blr

L(byte_loop):
       lbz     r5,0(r3)
       addi    r3,r3,1
       lbz     r6,0(r4)
       addi    r4,r4,1
       cmplw   r5,r6
       bne     L(st1)
       cmpwi   r5,0
       beq     L(end_strcmp)
       b       L(byte_loop)
END (strcmp)
libc_hidden_builtin_def (strcmp)