From baeae86fb8ccd85b6bf9b5091884fa9b66d84a99 Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Sun, 3 Jul 2022 21:28:06 -0700 Subject: x86: Add comment explaining no Slow_SSE4_2 check in ifunc-sse4_2 Just for clarities sake and so that if a future implementation is added we remember to add the check. --- sysdeps/x86_64/multiarch/ifunc-sse4_2.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'sysdeps/x86_64/multiarch') diff --git a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h index ee36525bcf..f8b56936ec 100644 --- a/sysdeps/x86_64/multiarch/ifunc-sse4_2.h +++ b/sysdeps/x86_64/multiarch/ifunc-sse4_2.h @@ -27,6 +27,12 @@ IFUNC_SELECTOR (void) { const struct cpu_features* cpu_features = __get_cpu_features (); + /* This function uses the `pcmpstri` sse4.2 instruction which can be + slow on some CPUs. This normally would be guarded by a + Slow_SSE4_2 check, but since there is no other optimized + implementation its best to keep it regardless. If an optimized + fallback is added add a X86_ISA_CPU_FEATURE_ARCH_P (cpu_features, + Slow_SSE4_2) check. */ if (CPU_FEATURE_USABLE_P (cpu_features, SSE4_2)) return OPTIMIZE (sse42); -- cgit 1.4.1