From 7e4ba49cd365555ddaff2ae8bba7b912464ad6e5 Mon Sep 17 00:00:00 2001 From: Harsha Jagasia Date: Fri, 4 Mar 2011 23:30:08 -0500 Subject: Enable SSE2 memset for AMD'supcoming Orochi processor. This patch enables SSE2 memset for AMD's upcoming Orochi processor. This patch also fixes the following bug: For misaligned blocks larger than > 144 Bytes, memset branches into the integer code path depending on the value of misalignment even if the startup code chooses the SSE2 code path upfront, when multiarch is enabled. --- sysdeps/x86_64/multiarch/init-arch.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'sysdeps/x86_64/multiarch') diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c index f0d2bb7d14..34ec2df2d5 100644 --- a/sysdeps/x86_64/multiarch/init-arch.c +++ b/sysdeps/x86_64/multiarch/init-arch.c @@ -1,6 +1,6 @@ /* Initialize CPU feature data. This file is part of the GNU C Library. - Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc. + Copyright (C) 2008, 2009, 2010, 2011 Free Software Foundation, Inc. Contributed by Ulrich Drepper . The GNU C Library is free software; you can redistribute it and/or @@ -60,7 +60,7 @@ __init_cpu_features (void) get_common_indeces (&family, &model); /* Intel processors prefer SSE instruction for memory/string - routines if they are avaiable. */ + routines if they are available. */ __cpu_features.feature[index_Prefer_SSE_for_memop] |= bit_Prefer_SSE_for_memop; @@ -107,6 +107,14 @@ __init_cpu_features (void) kind = arch_kind_amd; get_common_indeces (&family, &model); + + unsigned int ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx; + + /* AMD processors prefer SSE instructions for memory/string routines + if they are available, otherwise they prefer integer instructions. */ + if ((ecx & 0x200)) + __cpu_features.feature[index_Prefer_SSE_for_memop] + |= bit_Prefer_SSE_for_memop; } else kind = arch_kind_other; -- cgit 1.4.1