From e59ced238482fd71f3e493717f14f6507346741e Mon Sep 17 00:00:00 2001 From: Noah Goldstein Date: Mon, 20 Sep 2021 16:20:15 -0500 Subject: x86: Optimize memset-vec-unaligned-erms.S No bug. Optimization are 1. change control flow for L(more_2x_vec) to fall through to loop and jump for L(less_4x_vec) and L(less_8x_vec). This uses less code size and saves jumps for length > 4x VEC_SIZE. 2. For EVEX/AVX512 move L(less_vec) closer to entry. 3. Avoid complex address mode for length > 2x VEC_SIZE 4. Slightly better aligning code for the loop from the perspective of code size and uops. 5. Align targets so they make full use of their fetch block and if possible cache line. 6. Try and reduce total number of icache lines that will need to be pulled in for a given length. 7. Include "local" version of stosb target. For AVX2/EVEX/AVX512 jumping to the stosb target in the sse2 code section will almost certainly be to a new page. The new version does increase code size marginally by duplicating the target but should get better iTLB behavior as a result. test-memset, test-wmemset, and test-bzero are all passing. Signed-off-by: Noah Goldstein Reviewed-by: H.J. Lu --- sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S') diff --git a/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S index 640f092903..64b09e77cc 100644 --- a/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S @@ -1,11 +1,18 @@ #if IS_IN (libc) +# define USE_WITH_EVEX 1 + # define VEC_SIZE 32 +# define MOV_SIZE 6 +# define RET_SIZE 1 + # define XMM0 xmm16 # define YMM0 ymm16 # define VEC0 ymm16 # define VEC(i) VEC##i -# define VMOVU vmovdqu64 -# define VMOVA vmovdqa64 + +# define VMOVU vmovdqu64 +# define VMOVA vmovdqa64 + # define VZEROUPPER # define MEMSET_VDUP_TO_VEC0_AND_SET_RETURN(d, r) \ -- cgit 1.4.1