From 3e9099b4f6666cd05b62d2829f65161daddb151b Mon Sep 17 00:00:00 2001 From: Ulrich Drepper Date: Thu, 23 Jul 2009 13:42:46 -0700 Subject: Add more cache descriptors for L3 caches on x86 and x86-64. The most recent AP 485 describes a few more cache descriptors for L3 caches with 24-way associativity. --- sysdeps/x86_64/cacheinfo.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'sysdeps/x86_64/cacheinfo.c') diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index 362687c181..07939099b9 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -100,6 +100,9 @@ static const struct intel_02_cache_info { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 2097152 }, { 0xe3, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 4194304 }, { 0xe4, 16, 64, M(_SC_LEVEL3_CACHE_SIZE), 8388608 }, + { 0xea, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 12582912 }, + { 0xeb, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 18874368 }, + { 0xec, 24, 64, M(_SC_LEVEL3_CACHE_SIZE), 25165824 }, }; #define nintel_02_known (sizeof (intel_02_known) / sizeof (intel_02_known [0])) -- cgit 1.4.1