From 8aa92022e2e7cb5470b6e252020140c05b8013ed Mon Sep 17 00:00:00 2001 From: Andrew Senkevich Date: Thu, 18 Jun 2015 17:04:07 +0300 Subject: Vector powf for x86_64 and tests. Here is implementation of vectorized powf containing SSE, AVX, AVX2 and AVX512 versions according to Vector ABI . * sysdeps/unix/sysv/linux/x86_64/libmvec.abilist: New symbols added. * sysdeps/x86/fpu/bits/math-vector.h: Added SIMD declaration and asm redirections for powf. * sysdeps/x86_64/fpu/Makefile (libmvec-support): Added new files. * sysdeps/x86_64/fpu/Versions: New versions added. * sysdeps/x86_64/fpu/libm-test-ulps: Regenerated. * sysdeps/x86_64/fpu/multiarch/Makefile (libmvec-sysdep_routines): Added build of SSE, AVX2 and AVX512 IFUNC versions. * sysdeps/x86_64/fpu/svml_s_wrapper_impl.h: Added 2 argument wrappers. * sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_powf4_core_sse4.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core.S: New file. * sysdeps/x86_64/fpu/multiarch/svml_s_powf8_core_avx2.S: New file. * sysdeps/x86_64/fpu/svml_s_powf16_core.S: New file. * sysdeps/x86_64/fpu/svml_s_powf4_core.S: New file. * sysdeps/x86_64/fpu/svml_s_powf8_core.S: New file. * sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S: New file. * sysdeps/x86_64/fpu/svml_s_powf_data.S: New file. * sysdeps/x86_64/fpu/svml_s_powf_data.h: New file. * sysdeps/x86_64/fpu/test-float-vlen16-wrappers.c: Vector powf tests. * sysdeps/x86_64/fpu/test-float-vlen16.c: Likewise. * sysdeps/x86_64/fpu/test-float-vlen4-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-float-vlen4.c: Likewise. * sysdeps/x86_64/fpu/test-float-vlen8-avx2-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-float-vlen8-avx2.c: Likewise. * sysdeps/x86_64/fpu/test-float-vlen8-wrappers.c: Likewise. * sysdeps/x86_64/fpu/test-float-vlen8.c: Likewise. * math/test-float-vlen16.h: Fixed 2 argument macro. * math/test-float-vlen4.h: Likewise. * math/test-float-vlen8.h: Likewise. * NEWS: Mention addition of x86_64 vector powf. --- sysdeps/x86/fpu/bits/math-vector.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'sysdeps/x86/fpu') diff --git a/sysdeps/x86/fpu/bits/math-vector.h b/sysdeps/x86/fpu/bits/math-vector.h index a5317b9e32..9e53bdf05d 100644 --- a/sysdeps/x86/fpu/bits/math-vector.h +++ b/sysdeps/x86/fpu/bits/math-vector.h @@ -46,6 +46,8 @@ # define __DECL_SIMD_expf __DECL_SIMD_x86_64 # undef __DECL_SIMD_pow # define __DECL_SIMD_pow __DECL_SIMD_x86_64 +# undef __DECL_SIMD_powf +# define __DECL_SIMD_powf __DECL_SIMD_x86_64 /* Workaround to exclude unnecessary symbol aliases in libmvec while GCC creates the vector names based on scalar asm name. @@ -71,6 +73,10 @@ __asm__ ("_ZGVbN2vv___pow_finite = _ZGVbN2vv_pow"); __asm__ ("_ZGVcN4vv___pow_finite = _ZGVcN4vv_pow"); __asm__ ("_ZGVdN4vv___pow_finite = _ZGVdN4vv_pow"); __asm__ ("_ZGVeN8vv___pow_finite = _ZGVeN8vv_pow"); +__asm__ ("_ZGVbN4vv___powf_finite = _ZGVbN4vv_powf"); +__asm__ ("_ZGVcN8vv___powf_finite = _ZGVcN8vv_powf"); +__asm__ ("_ZGVdN8vv___powf_finite = _ZGVdN8vv_powf"); +__asm__ ("_ZGVeN16vv___powf_finite = _ZGVeN16vv_powf"); # endif #endif -- cgit 1.4.1