From 559398ab746fd7dbbe09e847813a1b917b9ded14 Mon Sep 17 00:00:00 2001 From: "David S. Miller" Date: Thu, 15 Mar 2012 00:11:17 -0700 Subject: Add more sparc VIS3 optimized math routines. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceil.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_ceilf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finite-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finite.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_finitef.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floor.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_floorf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isinff.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnan.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_isnanf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrint.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_lrintf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rint-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rint.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf-vis3.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/s_rintf.S: New file. * sysdeps/sparc/sparc64/fpu/multiarch/Makefile: Add new VIS3 routines. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S: New file. * sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile: Add new VIS3 routines. * sysdeps/sparc/sparc32/sparcv9/fpu/unix/sysv/linux/multiarch/Implies: New file. --- .../sparc/sparc32/sparcv9/fpu/multiarch/Makefile | 10 +-- .../sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S | 78 +++++++++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S | 74 ++++++++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S | 26 +++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S | 26 +++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S | 79 ++++++++++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S | 74 ++++++++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S | 58 ++++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S | 51 ++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S | 54 +++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_llrintf.S | 51 ++++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S | 55 +++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S | 51 ++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S | 49 ++++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S | 46 +++++++++++++ .../sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S | 47 +++++++++++++ .../sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S | 46 +++++++++++++ 25 files changed, 1238 insertions(+), 5 deletions(-) create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S create mode 100644 sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S (limited to 'sysdeps/sparc/sparc32/sparcv9/fpu/multiarch') diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile index 33b03ac6aa..3a7a389380 100644 --- a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/Makefile @@ -1,9 +1,9 @@ ifeq ($(subdir),math) ifeq ($(have-as-vis3),yes) -libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 +libm-sysdep_routines += m_copysignf-vis3 m_copysign-vis3 s_ceilf-vis3 \ + s_ceil-vis3 s_fabs-vis3 s_fabsf-vis3 s_floor-vis3 \ + s_floorf-vis3 s_llrintf-vis3 s_llrint-vis3 \ + s_rintf-vis3 s_rint-vis3 w_sqrt-vis3 w_sqrtf-vis3 sysdep_routines += s_copysignf-vis3 s_copysign-vis3 - -CFLAGS-s_copysignf-vis3.S = -Wa,-Av9d -CFLAGS-s_copysign-vis3.S = -Wa,-Av9d endif -endif \ No newline at end of file +endif diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S new file mode 100644 index 0000000000..be41219cef --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil-vis3.S @@ -0,0 +1,78 @@ +/* ceil function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceil_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + sethi %hi(ONE_DOT_ZERO), %o3 + or %o0, %o1, %o0 + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fzero ZERO + sllx %o3, 32, %o3 + + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovduge %fcc2, ZERO, %f20 + faddd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__ceil_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S new file mode 100644 index 0000000000..f91fda61b9 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceil.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__ceil) + .type __ceil, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceil_vis3), %o1 + xor %o1, %gdop_lox10(__ceil_vis3), %o1 +# else + set __ceil_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceil_generic), %o1 + xor %o1, %gdop_lox10(__ceil_generic), %o1 +# else + set __ceil_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceil) +weak_alias (__ceil, ceil) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceil __ceil_generic + +#include "../s_ceil.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S new file mode 100644 index 0000000000..c35a85f24f --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf-vis3.S @@ -0,0 +1,74 @@ +/* Float ceil function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__ceilf_vis3) + movwtos %o0, %f0 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f0, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f0, %f16, %f1 + fsubs %f1, %f16, %f1 + fcmps %fcc2, %f1, %f0 + movwtos %o3, %f9 + + fmovsuge %fcc2, ZERO, %f9 + fadds %f1, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__ceilf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S new file mode 100644 index 0000000000..048b6195d8 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_ceilf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__ceilf) + .type __ceilf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__ceilf_vis3), %o1 + xor %o1, %gdop_lox10(__ceilf_vis3), %o1 +# else + set __ceilf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__ceilf_generic), %o1 + xor %o1, %gdop_lox10(__ceilf_generic), %o1 +# else + set __ceilf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__ceilf) +weak_alias (__ceilf, ceilf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __ceilf __ceilf_generic + +#include "../s_ceilf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S new file mode 100644 index 0000000000..733ec90e42 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32+v9 vis3 version. + Copyright (C) 2011 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__fabs_vis3) + movwtos %o0, %f0 + movwtos %o1, %f1 + retl + fabsd %f0, %f0 +END (__fabs_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S new file mode 100644 index 0000000000..ed70e4be2c --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabs.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__fabs) + .type __fabs, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__fabs_vis3), %o1 + xor %o1, %gdop_lox10(__fabs_vis3), %o1 +# else + set __fabs_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__fabs_generic), %o1 + xor %o1, %gdop_lox10(__fabs_generic), %o1 +# else + set __fabs_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__fabs) +weak_alias (__fabs, fabs) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabs __fabs_generic + +#include "../s_fabs.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S new file mode 100644 index 0000000000..82b577580e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf-vis3.S @@ -0,0 +1,26 @@ +/* Float absolute value, sparc32 vis3 version. + Copyright (C) 2006 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Jakub Jelinek , 2006. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__fabsf_vis3) + movwtos %o0, %f0 + retl + fabss %f0, %f0 +END (__fabsf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S new file mode 100644 index 0000000000..4b7351fc2e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_fabsf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__fabsf) + .type __fabsf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__fabsf_vis3), %o1 + xor %o1, %gdop_lox10(__fabsf_vis3), %o1 +# else + set __fabsf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__fabsf_generic), %o1 + xor %o1, %gdop_lox10(__fabsf_generic), %o1 +# else + set __fabsf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__fabsf) +weak_alias (__fabsf, fabsf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __fabsf __fabsf_generic + +#include "../../../fpu/s_fabsf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S new file mode 100644 index 0000000000..d7e5d24c17 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor-vis3.S @@ -0,0 +1,79 @@ +/* floor function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ +#define ONE_DOT_ZERO 0x3ff00000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floor_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + sethi %hi(ONE_DOT_ZERO), %o3 + or %o0, %o1, %o0 + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fzero ZERO + sllx %o3, 32, %o3 + + fnegd ZERO, SIGN_BIT + + stx %o2, [%sp + 72] + fabsd %f0, %f14 + + ldd [%sp + 72], %f16 + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f18 + fsubd %f18, %f16, %f18 + fcmpd %fcc2, %f18, %f0 + movxtod %o3, %f20 + + fmovdule %fcc2, ZERO, %f20 + fsubd %f18, %f20, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__floor_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S new file mode 100644 index 0000000000..1cdc53fb84 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floor.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__floor) + .type __floor, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floor_vis3), %o1 + xor %o1, %gdop_lox10(__floor_vis3), %o1 +# else + set __floor_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floor_generic), %o1 + xor %o1, %gdop_lox10(__floor_generic), %o1 +# else + set __floor_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floor) +weak_alias (__floor, floor) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floor __floor_generic + +#include "../s_floor.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S new file mode 100644 index 0000000000..24c8764fa6 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf-vis3.S @@ -0,0 +1,74 @@ +/* Float floor function, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* Since changing the rounding mode is extremely expensive, we + try to round up using a method that is rounding mode + agnostic. + + We add then subtract (or subtract than add if the initial + value was negative) 2**23 to the value, then subtract it + back out. + + This will clear out the fractional portion of the value. + One of two things will happen for non-whole initial values. + Either the rounding mode will round it up, or it will be + rounded down. If the value started out whole, it will be + equal after the addition and subtraction. This means we + can accurately detect with one test whether we need to add + another 1.0 to round it up properly. + + VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ +#define ONE_DOT_ZERO 0x3f800000 /* 1.0 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__floorf_vis3) + movwtos %o0, %f0 + sethi %hi(TWO_TWENTYTHREE), %o2 + sethi %hi(ONE_DOT_ZERO), %o3 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f0, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f0, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f0, %f16, %f1 + fsubs %f1, %f16, %f1 + fcmps %fcc2, %f1, %f0 + movwtos %o3, %f9 + + fmovsule %fcc2, ZERO, %f9 + fsubs %f1, %f9, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__floorf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S new file mode 100644 index 0000000000..0dcd0e1431 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_floorf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__floorf) + .type __floorf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__floorf_vis3), %o1 + xor %o1, %gdop_lox10(__floorf_vis3), %o1 +# else + set __floorf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__floorf_generic), %o1 + xor %o1, %gdop_lox10(__floorf_generic), %o1 +# else + set __floorf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__floorf) +weak_alias (__floorf, floorf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __floorf __floorf_generic + +#include "../s_floorf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S new file mode 100644 index 0000000000..8a90722b54 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint-vis3.S @@ -0,0 +1,58 @@ +/* llrint(), sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + for %f0, SIGN_BIT, %f0 + fdtox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrint_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S new file mode 100644 index 0000000000..3a9294d3a8 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrint.S @@ -0,0 +1,51 @@ +#include + + .text +ENTRY(__llrint) + .type __llrint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__llrint_vis3), %o1 + xor %o1, %gdop_lox10(__llrint_vis3), %o1 +# else + set __llrint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__llrint_generic), %o1 + xor %o1, %gdop_lox10(__llrint_generic), %o1 +# else + set __llrint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__llrint) +weak_alias (__llrint, llrint) + +strong_alias (__llrint, __lllrint) +weak_alias (__lllrint, lllrint) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrint __llrint_generic + +#include "../s_llrint.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S new file mode 100644 index 0000000000..8590af2bb4 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf-vis3.S @@ -0,0 +1,54 @@ +/* llrintf(), sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__llrintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + fors %f0, SIGN_BIT, %f0 + fstox %f0, %f4 + movstouw %f4, %o0 + retl + movstouw %f5, %o1 +END (__llrintf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S new file mode 100644 index 0000000000..f2236f0eec --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_llrintf.S @@ -0,0 +1,51 @@ +#include + + .text +ENTRY(__llrintf) + .type __llrintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__llrintf_vis3), %o1 + xor %o1, %gdop_lox10(__llrintf_vis3), %o1 +# else + set __llrintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__llrintf_generic), %o1 + xor %o1, %gdop_lox10(__llrintf_generic), %o1 +# else + set __llrintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__llrintf) +weak_alias (__llrintf, llrintf) + +strong_alias (__llrintf, __lllrintf) +weak_alias (__lllrintf, lllrintf) + +# undef weak_alias +# define weak_alias(a, b) +# undef strong_alias +# define strong_alias(a, b) + +#define __llrintf __llrintf_generic + +#include "../s_llrintf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S new file mode 100644 index 0000000000..6c4a3e00dd --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint-vis3.S @@ -0,0 +1,55 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_FIFTYTWO 0x43300000 /* 2**52 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rint_vis3) + sethi %hi(TWO_FIFTYTWO), %o2 + sllx %o0, 32, %o0 + + or %o0, %o1, %o0 + fzero ZERO + + movxtod %o0, %f0 + sllx %o2, 32, %o2 + fnegd ZERO, SIGN_BIT + + movxtod %o2, %f16 + fabsd %f0, %f14 + + fcmpd %fcc3, %f14, %f16 + + fmovduge %fcc3, ZERO, %f16 + fand %f0, SIGN_BIT, SIGN_BIT + + for %f16, SIGN_BIT, %f16 + faddd %f0, %f16, %f6 + fsubd %f6, %f16, %f0 + fabsd %f0, %f0 + retl + for %f0, SIGN_BIT, %f0 +END (__rint_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S new file mode 100644 index 0000000000..3872ae299e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rint.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__rint) + .type __rint, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rint_vis3), %o1 + xor %o1, %gdop_lox10(__rint_vis3), %o1 +# else + set __rint_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rint_generic), %o1 + xor %o1, %gdop_lox10(__rint_generic), %o1 +# else + set __rint_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rint) +weak_alias (__rint, rint) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rint __rint_generic + +#include "../s_rint.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S new file mode 100644 index 0000000000..ec0bb37b13 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf-vis3.S @@ -0,0 +1,51 @@ +/* Round float to int floating-point values, sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by David S. Miller , 2012. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + + /* VIS instructions are used to facilitate the formation of + easier constants, and the propagation of the sign bit. */ + +#define TWO_TWENTYTHREE 0x4b000000 /* 2**23 */ + +#define ZERO %f10 /* 0.0 */ +#define SIGN_BIT %f12 /* -0.0 */ + +ENTRY (__rintf_vis3) + movwtos %o0, %f1 + sethi %hi(TWO_TWENTYTHREE), %o2 + fzeros ZERO + + fnegs ZERO, SIGN_BIT + + movwtos %o2, %f16 + fabss %f1, %f14 + + fcmps %fcc3, %f14, %f16 + + fmovsuge %fcc3, ZERO, %f16 + fands %f1, SIGN_BIT, SIGN_BIT + + fors %f16, SIGN_BIT, %f16 + fadds %f1, %f16, %f5 + fsubs %f5, %f16, %f0 + fabss %f0, %f0 + retl + fors %f0, SIGN_BIT, %f0 +END (__rintf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S new file mode 100644 index 0000000000..9918929220 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/s_rintf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__rintf) + .type __rintf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__rintf_vis3), %o1 + xor %o1, %gdop_lox10(__rintf_vis3), %o1 +# else + set __rintf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__rintf_generic), %o1 + xor %o1, %gdop_lox10(__rintf_generic), %o1 +# else + set __rintf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__rintf) +weak_alias (__rintf, rintf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __rintf __rintf_generic + +#include "../s_rintf.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S new file mode 100644 index 0000000000..3880da0d8e --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt-vis3.S @@ -0,0 +1,49 @@ +/* sqrt function. sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__sqrt_vis3) + movwtos %o0, %f0 + fzero %f8 + movwtos %o1, %f1 + fcmpd %f0, %f8 + fbl 1f + nop +8: retl + fsqrtd %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o2 + mov %o1, %o3 + mov 26, %o4 + mov %o7, %g1 + call __kernel_standard + mov %g1, %o7 +END (__sqrt_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S new file mode 100644 index 0000000000..80b15767ce --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrt.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__sqrt) + .type __sqrt, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__sqrt_vis3), %o1 + xor %o1, %gdop_lox10(__sqrt_vis3), %o1 +# else + set __sqrt_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__sqrt_generic), %o1 + xor %o1, %gdop_lox10(__sqrt_generic), %o1 +# else + set __sqrt_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__sqrt) +weak_alias (__sqrt, sqrt) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrt __sqrt_generic + +#include "../w_sqrt.S" diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S new file mode 100644 index 0000000000..2d4270f9cd --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf-vis3.S @@ -0,0 +1,47 @@ +/* sqrtf function. sparc32 v9 vis3 version. + Copyright (C) 2012 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +ENTRY (__sqrtf_vis3) + movwtos %o0, %f0 + fzeros %f8 + fcmps %f0, %f8 + fbl 1f + nop +8: retl + fsqrts %f0, %f0 +1: +#ifdef SHARED + SETUP_PIC_REG_LEAF(o5, g1) + sethi %gdop_hix22(_LIB_VERSION), %g1 + xor %g1, %gdop_lox10(_LIB_VERSION), %g1 + ld [%o5 + %g1], %g1, %gdop(_LIB_VERSION) +#else + sethi %hi(_LIB_VERSION), %g1 + or %g1, %lo(_LIB_VERSION), %g1 +#endif + ld [%g1], %g1 + cmp %g1, -1 + be 8b + mov %o0, %o1 + mov 126, %o2 + mov %o7, %g1 + call __kernel_standard_f + mov %g1, %o7 +END (__sqrtf_vis3) diff --git a/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S new file mode 100644 index 0000000000..a700a4e876 --- /dev/null +++ b/sysdeps/sparc/sparc32/sparcv9/fpu/multiarch/w_sqrtf.S @@ -0,0 +1,46 @@ +#include + + .text +ENTRY(__sqrtf) + .type __sqrtf, @gnu_indirect_function +# ifdef SHARED + SETUP_PIC_REG_LEAF(o3, o5) +# endif +# ifdef HAVE_AS_VIS3_SUPPORT + set HWCAP_SPARC_VIS3, %o1 + andcc %o0, %o1, %g0 + be 9f + nop +# ifdef SHARED + sethi %gdop_hix22(__sqrtf_vis3), %o1 + xor %o1, %gdop_lox10(__sqrtf_vis3), %o1 +# else + set __sqrtf_vis3, %o1 +# endif + ba 10f + nop +9: +# endif +# ifdef SHARED + sethi %gdop_hix22(__sqrtf_generic), %o1 + xor %o1, %gdop_lox10(__sqrtf_generic), %o1 +# else + set __sqrtf_generic, %o1 +# endif +# ifdef HAVE_AS_VIS3_SUPPORT +10: +# endif +# ifdef SHARED + add %o3, %o1, %o1 +# endif + retl + mov %o1, %o0 +END(__sqrtf) +weak_alias (__sqrtf, sqrtf) + +# undef weak_alias +# define weak_alias(a, b) + +#define __sqrtf __sqrtf_generic + +#include "../w_sqrtf.S" -- cgit 1.4.1