From 487972aea52004f604c2878c8c9d3e77670f2c32 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Thu, 27 Feb 2014 09:43:51 -0600 Subject: PowerPC: Optimized isnan/isnanf for POWER8 This patch add a optimized isnan/isnanf implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move. --- sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S | 1 + 1 file changed, 1 insertion(+) create mode 100644 sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S (limited to 'sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S') diff --git a/sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S new file mode 100644 index 0000000000..b48c85e0d3 --- /dev/null +++ b/sysdeps/powerpc/powerpc64/power8/fpu/s_isnanf.S @@ -0,0 +1 @@ +/* This function uses the same code as s_isnan.S. */ -- cgit 1.4.1