From 1ea339b69725cb2f30b5a84cb7ca96111c9a637b Mon Sep 17 00:00:00 2001 From: Torvald Riegel Date: Sat, 18 Oct 2014 01:02:59 +0200 Subject: Add arch-specific configuration for C11 atomics support. This sets __HAVE_64B_ATOMICS if provided. It also sets USE_ATOMIC_COMPILER_BUILTINS to true if the existing atomic ops use the __atomic* builtins (aarch64, mips partially) or if this has been tested (x86_64); otherwise, this is set to false so that C11 atomics will be based on the existing atomic operations. --- sysdeps/microblaze/bits/atomic.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'sysdeps/microblaze/bits') diff --git a/sysdeps/microblaze/bits/atomic.h b/sysdeps/microblaze/bits/atomic.h index 77004a0284..395162df2d 100644 --- a/sysdeps/microblaze/bits/atomic.h +++ b/sysdeps/microblaze/bits/atomic.h @@ -35,6 +35,9 @@ typedef uintptr_t uatomicptr_t; typedef intmax_t atomic_max_t; typedef uintmax_t uatomic_max_t; +#define __HAVE_64B_ATOMICS 1 +#define USE_ATOMIC_COMPILER_BUILTINS 0 + /* Microblaze does not have byte and halfword forms of load and reserve and store conditional. So for microblaze we stub out the 8- and 16-bit forms. */ -- cgit 1.4.1